Bridge Die Stacked SiP for Compact Footprint
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor package technologies face challenges in reducing the size of system-in-packages (SiPs) while maintaining high performance, as integrating multiple semiconductor chips side-by-side complicates the reduction of SiP width and efficient data transmission between chips.
Innovation Solution
The implementation of a system-in-package design that includes a redistributed line (RDL) structure with a first semiconductor chip and a second semiconductor chip stacked on top, where the second chip protrudes past the first chip, supported by a bridge die with through vias that electrically connect the chips, and a molding layer to dissipate heat and surround the second chip, allowing for efficient electrical connections and reduced SiP size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are disposed side-by-side to increase package integration density, then the data transmission speed and multi-functional operation are improved, but the width of the SiP increases making it difficult to reduce the size
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side chip arrangement to a three-dimensional stacked configuration. Multiple semiconductor chips are vertically stacked and connected through through-vias, enabling high-speed data transmission while maintaining a compact footprint and reducing the overall width of the SiP package.
Solution Approach 2:
The patent implements a nested structure where smaller semiconductor chips are stacked within the vertical space occupied by larger chips below. This nesting approach allows multiple functional units to be integrated in a compact vertical arrangement, increasing package integration density without expanding the horizontal dimensions of the SiP.
2Length of stationary object
If the SiP size is reduced by stacking chips vertically, then the width is reduced, but the electrical connection complexity between chips increases
Solution Approach 1:
The patent segments the electrical connection paths into discrete through-vias that penetrate each chip layer. This segmentation allows for modular interconnection, where each via provides a dedicated electrical pathway between stacked chips, simplifying the overall connection architecture despite the vertical stacking configuration.
Solution Approach 2:
The patent introduces intermediate connection structures, including redistribution layers (RDL) and through-vias, that mediate between the chip pads and external connections. These intermediary elements simplify the electrical connection complexity by providing standardized interfaces and routing paths between stacked chips.
3Productivity
If chips are stacked with protrusions to increase integration density, then the package size is reduced, but the structural stability and support requirements increase
Solution Approach 1:
The patent employs composite structural designs combining different materials with complementary properties. The package structure integrates chips with protrusions, support elements, and encapsulation materials to create a composite assembly that maintains structural stability while achieving high integration density through vertical stacking.
Solution Approach 2:
The patent incorporates support structures and cushioning elements in advance to prevent structural failures. The protrusions are designed with built-in support mechanisms that provide mechanical reinforcement before assembly, ensuring structural stability throughout the stacking process and during operation.
Data Source
AI summary
A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die.