Bridge Device DMA Reset for Tag Overlap Prevention
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Solution Overview
Problem
Current data transferring methods experience significant speed reductions due to tag identification overlapping when data packet failures occur, leading to prolonged pauses in external storage device operations.
Innovation Solution
A bridge device with a physical layer circuit, buffer memory, and DMA controller, which resets the buffer memory and DMA controller upon receiving a clear feature command from an upstream device, preventing tag ID overlap by removing uncompleted command information units and resetting data transfer operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer restarts after a packet failure, then data transmission continues, but tag identification overlapping occurs and reading/writing speed significantly lowers
Solution Approach 1:
The system performs preliminary actions by clearing the endpoint halt status and resetting the buffer memory and DMA controller before restarting data transmission. This preliminary reset operation ensures that tag identifiers are properly reinitialized, preventing tag identification overlapping that would otherwise occur during restart operations.
Solution Approach 2:
The system implements feedback mechanisms through the clear feature command that triggers a reset sequence. When a packet failure is detected, the system receives feedback in the form of an endpoint halt status, which then triggers the buffer memory and DMA controller reset operations to correct the tag identification issue before resuming transmission.
2Reliability
If buffer memory and DMA controller are reset to prevent tag overlap, then tag identification accuracy improves, but data transferring operation is interrupted
Solution Approach 1:
The system rushes through the reset operation by clearing the endpoint halt status and resetting the buffer memory and DMA controller in a rapid sequence upon detecting a packet failure. This minimizes the interruption time while ensuring that tag identification accuracy is restored, allowing the system to quickly skip past the error state and resume normal operations.
3Reliability
If clear feature command is processed to reset data transfer, then tag overlapping is prevented, but command processing complexity increases
Solution Approach 1:
The system extracts the reset functionality into a dedicated clear feature command handling routine. When a packet failure occurs, the endpoint halt status is cleared and the buffer memory and DMA controller are reset through a specialized command sequence, separating this error recovery function from the normal data transfer processing logic.
Data Source
AI summary
A bridge device includes a first physical layer circuit, a first buffer memory, a DMA controller, and a processor. The first physical layer circuit is configured to connect to an upstream device. The first buffer memory is configured to store a first data and transfer data to the upstream device via the first physical layer circuit. The DMA controller is coupled to the first buffer memory and configured to access the first data in the first buffer memory to read and/or write a storage device correspondingly. The processor is coupled to the first buffer memory and the DMA controller. When the bridge device receives a clear feature command from the upstream device, the processor is configured to reset the first buffer memory and the DMA controller to stop the data transferring between the upstream device and the bridge device.