Bridge-Interposer Semiconductor Package for Dense Chiplet Integration
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Solution Overview
Problem
Existing semiconductor packages, such as CoWoS structures, are not entirely satisfactory in terms of integration density and package size, particularly for advanced applications like cloud computing and data centers.
Innovation Solution
A semiconductor package design featuring chiplets on fan-out interposers with bridge structures and redistribution layers, allowing for improved integration density and reduced package size through the use of chiplets and interposers with varying critical dimensions, along with dielectric encapsulation and redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor packages are used, then manufacturing process is simpler, but integration density is insufficient and package size is larger
Solution Approach 1:
The semiconductor package is divided into multiple chiplets (first chiplet, second chiplet, third chiplet) that are separately manufactured and then integrated together. This segmentation allows each chiplet to be optimized independently while achieving high overall integration density when combined in the package substrate.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical integration by stacking chiplets at different heights on the package substrate. The first chiplet is positioned at a first height, the second chiplet at a second height, and the third chiplet at a third height, utilizing the vertical dimension to dramatically increase integration density without increasing footprint area.
2Area of stationary object
If package size is reduced, then area occupation decreases, but manufacturing precision requirements increase
Solution Approach 1:
The package substrate is prepared in advance with pre-formed connection regions, conductive vias, and bonding pads before chiplet placement. This preliminary preparation ensures that when chiplets are positioned at their specific heights and locations, precise electrical connections can be established without requiring post-placement alignment adjustments, thereby maintaining high precision in a compact package.
Solution Approach 2:
The package substrate serves as an intermediary platform that provides a standardized interface between multiple chiplets. The substrate's pre-configured connection regions and conductive structures mediate the complex interconnections between chiplets, allowing precise positioning and connection while keeping the overall package area small.
3Quantity of substance
If chiplets with varying critical dimensions are used, then integration density improves, but device complexity increases
Solution Approach 1:
Different regions of the package substrate are designed with locally optimized characteristics - connection regions for electrical connections, support regions for mechanical support, and routing regions for signal paths. Each chiplet region can have customized connection configurations matching its specific critical dimensions, allowing high integration density while managing complexity through localized design optimization.
Data Source
AI summary
A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.