Bridge-Layer Reservoir Capacitor Structure for Dense 3D Memory
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Solution Overview
Problem
Current three-dimensional semiconductor devices face challenges in increasing memory cell density and reducing parasitic capacitance, which affects their structural and performance characteristics.
Innovation Solution
The semiconductor device incorporates a lower structure with a vertical conductive line, a reservoir capacitor spaced apart from the conductive line, and a bridge horizontal layer between them, along with intersecting horizontal layers, fabricated using a method involving sacrificial layers and conductive materials to form a three-dimensional array of memory cells and reservoir capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor devices are used to increase memory cell density, then storage capacity is improved, but parasitic capacitance increases affecting performance
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional vertically stacked capacitor structures. Multiple capacitor stacks are arranged in the vertical dimension, allowing increased memory cell density without proportionally increasing parasitic capacitance, as the capacitors are distributed across multiple levels rather than occupying the same planar space
Solution Approach 2:
The memory device is divided into multiple independent capacitor stacks, each with its own conductive plate and dielectric layer. This segmentation allows the total capacitance to be distributed across multiple smaller units, reducing the parasitic capacitance contribution from any single large capacitor while maintaining the required total storage capacity
2Reliability
If complex three-dimensional structures are implemented to improve device performance, then functional characteristics are enhanced, but manufacturing complexity increases
Solution Approach 1:
Sacrificial layers are deposited and patterned beforehand to define the precise locations where capacitor stacks will be formed. These sacrificial structures guide subsequent processing steps, ensuring that the complex three-dimensional capacitor arrays are created at the correct positions without requiring complex real-time alignment procedures
Solution Approach 2:
Sacrificial layers serve as intermediary structures during fabrication. These temporary structures facilitate the formation of the complex capacitor stacks by providing a scaffold for dielectric and conductive material deposition, and are removed only after they have served their purpose in defining the final structure geometry
3Manufacturing precision
If sacrificial layers and replacement processes are used to form complex structures, then structural precision is improved, but manufacturing steps increase
Solution Approach 1:
Multiple processing operations are combined into single steps where possible. For example, the deposition of dielectric layers and conductive materials is performed in integrated sequences, and the removal of sacrificial layers is combined with the formation of the final capacitor structures, reducing the total number of discrete manufacturing steps while maintaining precision
Data Source
AI summary
A semiconductor device includes a lower structure; a vertical conductive line extending in a first direction which is perpendicular to a surface of the lower structure; a reservoir capacitor disposed over the lower structure to be spaced apart from the vertical conductive line; a bridge horizontal layer disposed between the vertical conductive line and the reservoir capacitor and extending horizontally in a second direction which is parallel to the surface of the lower structure; and a pair of horizontal layers extending in a third direction intersecting the bridge horizontal layer with the bridge horizontal layer interposed therebetween.