Redistribution Structure With Bridge Layer for Stacked Logic-Cache Dies
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in the design and manufacturing of smaller dies.
Innovation Solution
A semiconductor device design featuring a first die with a redistribution structure, a second die with a cache unit, and a third die with a cache unit, where the redistribution structure includes conductive layers and a bridge layer to electrically couple the dies, allowing cooperative operation and access to the first die, thereby enhancing performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If semiconductor devices are scaled down to meet increasing computing demand, then computing ability is improved, but quality, yield, performance, and reliability deteriorate while complexity increases
Solution Approach 1:
The patent divides the semiconductor device into multiple separate dies (first die, second die, third die) that are bonded together in a 3D stacked configuration. Each die can be independently manufactured and tested, improving yield and reliability while achieving higher computing capacity through parallel processing across multiple dies.
Solution Approach 2:
The patent transitions from a 2D planar layout to a 3D vertical stacked architecture. Multiple dies are arranged vertically with redistribution structures connecting different layers, enabling increased computing ability without further scaling down individual die dimensions, thus avoiding the reliability and manufacturing issues associated with extreme miniaturization.
2Power
If semiconductor devices are scaled down, then computing ability is improved, but manufacturing complexity increases
Solution Approach 1:
By segmenting the device into separate dies, each die can be manufactured using standard processes without requiring complex ultra-fine scaling. The redistribution structures are formed as distinct layers that can be independently patterned and connected, simplifying the overall manufacturing process while achieving high computing ability through 3D integration.
3Power
If multiple dies are integrated to improve performance, then computing ability is improved, but device complexity increases
Solution Approach 1:
The patent uses vertical stacking to integrate multiple dies in the third dimension, with redistribution structures organized in corresponding layers. This 3D arrangement allows multiple cache units and logic dies to be interconnected through vertical vias and conductive layers, achieving high computing ability while managing complexity through systematic layering and alignment.
Data Source
AI summary
The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and including a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and including a second cache unit. The first redistribution structure includes: a plurality of conductive layers electrically coupled the first die and the first cache unit and electrically coupled the first die and the second cache unit, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit and the second cache unit are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.