Heterogeneous Bridge Logic for Power Management
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Solution Overview
Problem
Current x86-based computing systems face challenges in minimizing power consumption while maintaining performance, especially in mobile devices, and lack seamless access to both x86 and ARM software applications, leading to inefficient battery life and complex power management.
Innovation Solution
A heterogeneous computer system is introduced, featuring an x86 core, a low-power hypervisor processor, and bridge logic that connects the hypervisor processor to the x86 core via the local bus, allowing the hypervisor processor to manage power states and translate processor languages, enabling efficient power conservation and simultaneous access to different OS applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a standard x86 processor is used to maintain high computing performance, then processing capability is improved, but power consumption increases
Solution Approach 1:
The system divides processing tasks between two processor types: a low-power ARM processor for basic operations and an x86 processor for computationally intensive tasks. This segmentation allows the system to optimize power consumption by using the appropriate processor for each task type, preventing the high-power x86 processor from running continuously while maintaining the ability to handle demanding workloads when needed.
2Use of energy by moving object
If ACPI power management modes are implemented in x86 systems, then power saving is improved, but system complexity and user configuration difficulty increase
Solution Approach 1:
The ARM processor automatically monitors system state and dynamically manages power allocation to the x86 processor without requiring user intervention or complex configuration. The system self-adjusts power states based on actual computational needs, eliminating the complexity of manual ACPI mode selection while achieving optimal power savings through automated decision-making.
3Adaptability or versatility
If virtual computing technology is used to access both x86 and non-x86 applications, then software compatibility is improved, but processing power consumption increases
Solution Approach 1:
The ARM processor serves as an intermediary that natively executes non-x86 applications while the x86 processor handles x86 applications directly. This eliminates the need for software-based virtualization of the entire system, as each processor type runs its native applications directly. The ARM processor acts as a mediator providing access to both application ecosystems without the overhead of full system emulation, significantly reducing power consumption compared to software virtualization approaches.
4Adaptability or versatility
If an x86-based smart mobile device is designed, then access to x86 software base is improved, but battery life decreases
Solution Approach 1:
The mobile device uses segmented processing where the low-power ARM processor handles everyday mobile tasks and light applications, reserving the high-power x86 processor for demanding computational tasks that require its capabilities. This segmentation enables the device to access the extensive x86 software base when needed while spending most operational time in low-power mode, achieving extended battery life comparable to or exceeding pure ARM devices while maintaining x86 application compatibility.
Data Source
AI summary
A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.