Bridge Logic Power Management for Processor Memory Traffic
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Solution Overview
Problem
Current power management techniques, such as OS-directed configuration and BIOS-controlled clock frequency for CPUs and RAM, are inefficient and can reduce CPU performance due to high workload and excessive power consumption, especially when dealing with varying memory access workloads.
Innovation Solution
A bridge logic system with a buffer, analyzer, and power management unit that monitors traffic load between the processor and main memory, adjusting operating clocks and voltage based on threshold values to manage power consumption without increasing CPU workload, employing a state machine to manage power performance trade-offs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If OS-directed configuration and power management is used to control processor performance states, then power consumption can be reduced, but CPU efficiency decreases due to heavy workload on the CPU
Solution Approach 1:
The patent extracts the power management function from the OS and implements it in the bridge logic chip. The bridge logic independently monitors CPU traffic load and controls processor performance states without OS intervention, thereby reducing CPU workload while maintaining power management capabilities
Solution Approach 2:
The bridge logic acts as an intermediary between the processor and main memory, and also as an intermediary for power management control. It monitors traffic load and directly controls processor performance states, mediating between system performance and power consumption without requiring OS involvement
2Use of energy by moving object
If aggressive power management is performed by the OS, then power saving is improved, but CPU performance is adversely affected due to frequent activities
Solution Approach 1:
The patent removes aggressive power management activities from the OS and implements them in the bridge logic. The bridge logic continuously monitors CPU traffic load and dynamically adjusts processor performance states, achieving aggressive power savings without burdening the CPU
3Speed
If main memory operates at high clock frequency to handle frequently serving access activities, then access efficiency is improved, but power consumption increases excessively
Solution Approach 1:
The patent implements dynamic clock frequency adjustment for main memory based on actual access workload. The bridge logic monitors memory access patterns and dynamically changes memory clock frequency to match the workload, achieving high efficiency during peak times while saving power during low-utilization periods
Solution Approach 2:
The patent changes the operating parameters of main memory (clock frequency) based on monitored traffic load. When access activities are frequent, memory operates at high frequency; when activities are infrequent, frequency is reduced, optimizing the balance between performance and power consumption
Data Source
AI summary
A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the state machine.