Bridge Offloads Memory Diagnosis from Slow Control Bus
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Solution Overview
Problem
The slow speed of the control complex bus in network processor systems limits the efficiency of memory diagnosis and data loading, particularly due to the need for data verification which requires two passes across the bus, leading to bottlenecks and increased complexity.
Innovation Solution
A bridge between the control complex bus and the PCI bus, implemented as an FPGA, performs checksum verification and diagnosis by writing and reading data over the faster PCI bus, allowing the control complex to issue high-level commands and reducing data transfer over the slow control complex bus, thereby facilitating faster memory diagnosis and data loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control complex performs memory diagnosis and data loading directly, then verification can be ensured, but the slow control complex bus creates a bottleneck that reduces startup speed
Solution Approach 1:
The patent introduces a bridge as an intermediary device between the control complex and network processor memory. The bridge performs memory diagnosis and data verification operations directly, acting as a mediator that relieves the control complex bus from heavy data transfer loads. This allows verification to occur through the faster PCI bus while the control complex only exchanges command and status information, resolving the contradiction between reliable verification and fast startup.
2Reliability
If data is written to memory and then read back for verification over the control complex bus, then data integrity can be confirmed, but the two-pass transfer over the slow bus significantly increases loading time
Solution Approach 1:
The bridge serves as an intermediary that performs the time-consuming data writing and verification operations directly over the fast PCI bus. The control complex only needs to send a load command and receive a status indicator, eliminating the need for two-pass data transfer over the slow control complex bus while maintaining full verification capability.
Solution Approach 2:
The bridge creates a local copy of the data in its own memory space, allowing it to perform verification operations independently without requiring the control complex to read back the data. This copying mechanism enables the control complex to verify data integrity through status indicators rather than actual data comparison, dramatically reducing loading time.
3Productivity
If a boot loader ROM is added to the network processor to enable local booting, then startup speed can be improved, but the cost increases due to additional components
Solution Approach 1:
The bridge is designed as a multi-functional device that not only performs memory diagnosis and data loading but also provides boot capability. By making the bridge universal and capable of multiple functions, the patent eliminates the need for separate boot ROM components in the network processor, achieving fast startup without increasing manufacturing complexity or cost.
Data Source
AI summary
A method and apparatus are provided for facilitating access from a control system to the memory of a processor across two buses, one of which acts as a bottleneck to communication between the control system and the processor. A bridge between the two buses acts as an intermediary. The control system issues simple diagnosis and data loading verification commands across a slow bus to the bridge. The bridge then performs the data intensive tasks by communicating with the processor through a faster bus. The bridge writes and reads data to the processor, and generates checksums of the written and read data. The bridge then returns status information to the control system indicative of the comparison of the checksums. In the case of memory diagnosis, the control system need only issue a simple command to the bridge through the slower, which then diagnoses the memory through the fast bus by writing and reading data, and returns a status to the control system through the slow bus. In the case of verification of loading of data, the bridge generates a checksum of the written data and then generates of a checksum of the data it reads back from the processor through the fast bus, and returns a status to the control system through the slow bus.