Bridge Communication System for Memory Bandwidth Optimization
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Solution Overview
Problem
The existing memory systems face challenges in efficiently utilizing bandwidth due to the faster serial interface speed compared to memory interface speed, leading to increased load capacity and reduced memory interface speed when multiple memories are connected in parallel, necessitating a technique to reduce wire count and load capacity while maintaining high-speed communication.
Innovation Solution
A memory system employing a bridge communication system that uses pulse amplitude modulation (PAM) and multiplexing symbols to overlap data from multiple channels, with bridge circuits extracting and storing data, and inserting new data into multiplexing symbols to maintain data integrity and balance, thereby reducing the number of wires and load capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory interfaces are connected in parallel to increase load capacity, then the memory capacity increases, but the memory interface speed is reduced
Solution Approach 1:
A bridge circuit is introduced as an intermediary component between the serial interface and multiple parallel memory interfaces. The bridge circuit receives serial data from the memory controller, demultiplexes it into multiple parallel data streams, and distributes them to multiple memory devices. This mediator enables the system to achieve both high-speed serial communication and increased memory capacity through parallel connections without directly coupling the speed degradation issue.
Solution Approach 2:
The data transmission is segmented into multiple parallel channels through the bridge circuit. Instead of using a single high-load memory interface, the system divides the data stream into multiple smaller parallel streams that can be handled by multiple memory interfaces simultaneously. This segmentation reduces the load on each individual interface while maintaining overall high data throughput.
2Speed
If multiple parallel memory interfaces are used to maintain high speed, then the communication speed is maintained, but the number of wires increases
Solution Approach 1:
Multiple parallel memory interfaces are merged into a single serial communication channel through the bridge circuit. The bridge circuit performs multiplexing in the reverse direction, combining multiple parallel data streams from memory devices into a single serial stream that can be transmitted over fewer wires back to the memory controller. This merging reduces wire count while maintaining the benefits of parallel memory access.
Solution Approach 2:
The system transitions from a two-dimensional parallel interface approach (multiple wires for multiple memory interfaces) to a time-multiplexed serial approach. By utilizing the time dimension through sequential transmission of parallel data streams, the system achieves equivalent data throughput with fewer spatial resources (wires), effectively adding a temporal dimension to the data transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces wire count and load capacity while maintaining high-speed communication by using PAM and multiplexing symbols to manage data transmission across multiple channels, ensuring data balance and integrity.
Implementation Method 1
A memory system employing a bridge communication system that uses pulse amplitude modulation (PAM) and multiplexing symbols to overlap data from multiple channels
Implementation Method 2
the first bridge circuit is configured to, upon receipt of the multiplexing symbols, extract the first data from the symbols
Data Source
AI summary
A memory system includes a first nonvolatile memory, a first bridge circuit connected to the memory, a second nonvolatile memory, a second bridge circuit connected to the second memory and connected to the first circuit, and a controller connected to the first circuit and configured to output, to the first circuit, first data to be stored in the first memory and second data to be stored in the second memory, the first and second data being mapped to multiplexing symbols. The first bridge circuit is configured to, upon receipt of the multiplexing symbols, extract the first data from the symbols, store the first data in the first memory, generate third data based on the second data to insert the generated third data into the multiplexing symbols where the first data was mapped, and output to the second circuit the multiplexing symbols into which the third data has been inserted.