Semiconductor Package With Bridge Memory Die

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor packaging technologies face limitations in integrating multiple logic dies and dual-port RAM within a single package, leading to suboptimal data transfer speeds and signal integrity between processors and memory.

Innovation Solution

A semiconductor package design that includes two logic dies and a bridge memory die, such as dual-port DRAM, in close proximity, with a redistribution layer and molding compound to enhance electrical coupling and reduce distance between memory and logic dies, allowing simultaneous addressing and improved inter-processor communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple logic dies and dual-port RAM are integrated in one package, then data transfer speed and signal integrity are improved, but device complexity increases

Engineering Contradiction:
Improvedata transfer speedVSAvoidpackage complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent combines multiple logic dies and dual-port RAM into a single semiconductor package, merging previously separate components into one integrated system. This consolidation enables direct data transfer between logic dies through the dual-port RAM, improving data transfer speed while managing complexity through unified package design

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The dual-port RAM acts as an intermediary component between the first and second logic dies, enabling direct communication and data transfer. This mediator approach allows high-speed data exchange without external circuit board connections, resolving the contradiction by providing speed improvement through the intermediary structure

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If logic dies are placed in close proximity, then inter-processor communication is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveinter-processor communication efficiencyVSAvoiddie placement precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

By placing logic dies in close proximity within the same package, the patent merges previously distant components into a compact arrangement. This enables direct data transfer and improved inter-processor communication efficiency, while the unified package structure manages the precision requirements through integrated manufacturing processes

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If dual-port RAM is used instead of single-port RAM, then data access capability is improved, but device complexity increases

Engineering Contradiction:
Improvememory access capabilityVSAvoidmemory structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The dual-port RAM provides multi-functionality by enabling simultaneous read/write operations at different addresses through different ports. This universal access capability allows the memory to serve multiple logic dies concurrently, improving adaptability and memory access capability while the integrated package design manages the structural complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10128212B2Semiconductor package and fabrication method thereof
Publication Date: 2018.11.13 MICRON TECHNOLOGY INC
  • US10128212B2 patent drawing
  • US10128212B2 patent drawing
  • US10128212B2 patent drawing

AI summary

A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. A redistribution layer (RDL) structure may be coupled to the first logic die, the second logic die, and the bridge memory die. The bridge memory die may be interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die and the RDL structure. A molding compound may at least partially encapsulate the first logic die, the second logic die, and the bridge memory die.