Bridge Module for Transparent L2 Cache Bypass in SOC

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Solution Overview

Problem

The design of a system on a chip (SOC) is complicated by the differing bandwidth and frequency requirements between the L2 cache and other components, such as the processing core, which creates challenges in interconnecting these components effectively.

Innovation Solution

A bridge module is introduced to selectively route information between the processing core, L2 cache, and bus interface unit (BIU), allowing for bypassing of the cache when necessary and enabling seamless communication regardless of cache presence or operability, thus acting as a bridge between components with different frequency and bandwidth needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the L2 cache is interconnected through the BIU like other SOC components, then the SOC structure is simplified, but the cache cannot meet its specific bandwidth and frequency requirements

Engineering Contradiction:

ImproveSOC interconnection structureVSAvoidL2 cache bandwidth and frequency performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

A bridge module is introduced as an intermediary component between the BIU and the L2 cache. The bridge module receives information from the BIU and selectively routes it to either the cache or the processing core based on cache status and information type, enabling the cache to operate at its required frequency and bandwidth while maintaining integration with the BIU through a standardized interface.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If the bridge module selectively routes information through the cache, then cache performance is optimized, but the system complexity increases due to additional routing logic

Engineering Contradiction:

ImproveL2 cache performanceVSAvoidbridge module routing logic

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The bridge module implements dynamic routing logic that adapts its behavior based on real-time conditions. It monitors cache presence, cache status (hit/miss), and information type (cacheable/non-cacheable) to dynamically select the appropriate routing path, thereby optimizing cache performance without requiring static complex routing structures.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The bridge module is divided into functional segments: a first bridge unit that receives information from the BIU, a second bridge unit that routes information to either the cache or processing core, and multiplexer units that select appropriate data paths. This segmentation simplifies the overall routing logic by distributing decision-making across modular components.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If the cache operates at a different frequency than the processing core, then the cache can be optimized for its specific workload, but interfacing between components becomes more difficult

Engineering Contradiction:

ImproveL2 cache frequency optimizationVSAvoidfrequency interface design

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The bridge module serves as a frequency intermediary between the BIU (operating at core frequency) and the L2 cache (operating at cache frequency). It handles frequency translation and timing synchronization, allowing the cache to operate at its optimized frequency while maintaining compatible interfaces with the rest of the SOC through the BIU.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8938585B1Transparent processing core and L2 cache connection

Publication Date: 2015.01.20 MARVELL ISRAEL (M L S L) LTD

AI summary

Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.