Bridge Output Circuit Dynamic Dead Time Control
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Solution Overview
Problem
The existing bridge output circuits require a significant dead time to prevent shoot-through current, which increases losses and inefficiencies in the circuit, necessitating a reduction in dead time while maintaining shoot-through current suppression.
Innovation Solution
A bridge output circuit design that includes detection circuits for transistor states and a gate control signal generation circuit to minimize dead time by adjusting the delay between transistor states, using an adjustment capacitor and delay circuit to generate control signals that ensure the transistors do not turn on simultaneously, thereby reducing the dead time period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dead time is increased to suppress shoot-through current, then reliability is improved, but loss of energy increases
Solution Approach 1:
The patent implements dynamic dead time adjustment by using detection circuits to monitor the actual on/off states of transistors and dynamically modifying the dead time period based on detected conditions. When transistors are detected to be in safe states, the dead time is reduced or eliminated, optimizing energy efficiency while maintaining shoot-through current suppression when needed.
Solution Approach 2:
The patent employs feedback mechanisms where detection circuits continuously monitor transistor states and feed this information back to the gate control signal generation circuit. This feedback enables the system to adjust the dead time period in real-time based on actual circuit conditions, preventing both shoot-through current and excessive energy loss.
2Reliability
If dead time is increased to prevent simultaneous transistor on-state, then reliability is improved, but productivity decreases
Solution Approach 1:
The system dynamically adjusts the dead time period based on real-time detection of transistor states. When transistors are detected to be safely off, the dead time is reduced, allowing for higher switching frequencies and improved productivity. This dynamic adjustment maintains reliability while optimizing switching performance.
Solution Approach 2:
The detection circuits automatically monitor transistor states and enable the gate control signal generation circuit to self-adjust the dead time period without external intervention. This self-service mechanism ensures reliable operation while maximizing switching frequency and productivity.
3Loss of energy
If dead time is minimized to reduce energy loss, then loss of energy is reduced, but reliability deteriorates
Solution Approach 1:
Feedback from detection circuits continuously monitors transistor states and provides real-time information to the gate control signal generation circuit. This feedback ensures that dead time is minimized only when transistor states confirm safety, preventing shoot-through current while reducing energy loss.
Solution Approach 2:
The patent changes the dead time parameter dynamically based on detected transistor states. When detection circuits confirm safe transistor operation, the dead time parameter is reduced or eliminated, minimizing energy loss while maintaining reliability through condition-based adjustment.
4Productivity
If complex detection and control circuits are added to reduce dead time, then productivity is improved, but device complexity increases
Solution Approach 1:
The detection circuits and gate control signal generation circuit are designed to perform multiple functions: detecting transistor states, determining dead time requirements, and generating appropriate control signals. This multi-functionality reduces the need for separate dedicated circuits, improving productivity while limiting complexity growth.
Solution Approach 2:
The patent merges the detection circuit functionality with the gate control signal generation circuit to create an integrated control system. By combining these functions into a unified structure, the system achieves high switching efficiency and productivity while avoiding the complexity of completely separate detection and control circuits.
Data Source
AI summary
A bridge output circuit of the present invention reduces the dead time.Upon receiving an input signal (SIN) for indicating on state of a high-side transistor (1H), a gate control signal generation circuit (4) outputs a low-side gate control signal (LGCTL) for turning off a low-side transistor (1L) to a low-side driver circuit (2L). On the other hand, a high-side gate control signal (HGCTL) for turning on the high-side transistor is generated from a signal delayed the low-side gate control signal and outputted to a high-side driver circuit (2H). The time of delay is controlled by the input signal (SIN), a signal (LGFB) indicating on/off state of the low-side transistor, and a signal (SOUT_L) indicating a level of an output signal.