Bridge Semiconductor Package Layout for Low-Warpage Multi-Chip Linking
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Solution Overview
Problem
Semiconductor packages with multiple chips face reliability issues due to thermal expansion mismatches, leading to stress and potential cracks as the package size increases, which decreases their reliability and processing speed.
Innovation Solution
A semiconductor package design featuring a redistribution line structure with bridge structures and a molding layer that electrically connects multiple semiconductor chips without an interposer, reducing thermal expansion-induced warpage and simplifying fabrication by eliminating the under-fill process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the semiconductor package includes multiple semiconductor chips to increase functionality, then the device complexity and functionality are improved, but the package size increases and thermal expansion mismatch stress increases leading to reliability degradation
Solution Approach 1:
The patent transitions from a planar arrangement of multiple chips to a three-dimensional stacked configuration. Multiple semiconductor chips are vertically stacked and connected through through-silicon-via (TSV) structures, allowing increased functionality without increasing the lateral package footprint. This vertical integration reduces thermal expansion mismatch stress by minimizing the horizontal area exposed to differential expansion forces.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically within a compact package body. The chips are arranged in layers with lower chips supporting upper chips, creating a nested configuration. This nesting approach allows multiple functional chips to be integrated in a small volume while reducing the overall package size and minimizing thermal stress through compact vertical arrangement.
2Adaptability or versatility
If the package size increases to accommodate multiple chips, then the functionality is improved, but the thermal expansion mismatch stress increases causing cracks and decreasing reliability
Solution Approach 1:
The patent employs vertical stacking in the third dimension to integrate multiple chips without increasing lateral package dimensions. This vertical arrangement reduces the horizontal area subject to thermal expansion mismatch, thereby decreasing the magnitude of thermal stress and the likelihood of crack formation in the package structure.
Solution Approach 2:
The patent utilizes a composite package structure consisting of multiple semiconductor chips with different material compositions stacked together. Each chip may have different coefficients of thermal expansion, but the vertical stacking configuration with controlled interface structures minimizes the cumulative thermal stress. The composite structure is designed to manage differential expansion through layered arrangement and interface engineering.
3Ease of manufacture
If traditional bonding wire or bump connections are used between chips, then the manufacturing process is simple, but the processing speed and data transmission efficiency are limited
Solution Approach 1:
The patent extracts and eliminates the traditional bonding wire or bump connection structures from the chip interconnection system. Instead, it implements direct vertical electrical connections through through-silicon-via (TSV) structures that penetrate through the chips. This extraction of the intermediate bonding layer reduces signal transmission distance and impedance, thereby increasing data processing speed while maintaining manufacturing feasibility through standardized TSV fabrication processes.
Solution Approach 2:
The patent introduces through-silicon-via (TSV) structures as intermediary conductive pathways between stacked chips. These TSV structures serve as direct electrical mediators that replace the indirect bonding wire/bump connections. The TSVs provide low-inductance, high-speed electrical pathways that enable faster data transmission between chips while maintaining a compact vertical architecture.
4Reliability
If an interposer is used to connect multiple chips, then the electrical connectivity is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts and eliminates the interposer component from the chip interconnection architecture. Instead of using a separate interposer substrate to facilitate electrical connections between chips, the invention implements direct vertical electrical connections through TSV structures that extend through the chips themselves. This extraction simplifies the overall device structure by removing an additional layer of complexity while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent merges the electrical connection function previously performed by a separate interposer directly into the chip structures themselves. The TSV structures are integrated within the chips and directly provide the electrical interconnection function, eliminating the need for a distinct interposer component. This merging reduces device complexity and the number of manufacturing steps while achieving the same electrical connectivity objective.
Data Source
AI summary
Provided is a semiconductor package. The semiconductor package includes a redistribution line structure comprising a plurality of redistribution line patterns; a first semiconductor chip and a second semiconductor chip on the redistribution line structure and spaced apart from each other; a bridge structure between the first semiconductor chip, the second semiconductor chip, and the redistribution line structure and comprising a plurality of connection wiring patterns configured to electrically connect the first semiconductor chip to the second semiconductor chip; and a molding layer surrounding a sidewall of the bridge structure and filled between the first semiconductor chip, the second semiconductor chip, and the redistribution line structure and between the first semiconductor chip and the second semiconductor chip, wherein lowermost surfaces of the plurality of connection wiring patterns are above uppermost surfaces of the plurality of redistribution line patterns.