Bridge-Pillar Segmented Interconnects for Low-Defect Semiconductor Routing
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Solution Overview
Problem
Increasing transistor density and decreasing device features in semiconductor manufacturing introduce manufacturing defects that affect device performance and functionality, particularly due to high-aspect ratio monolithic vias leading to fill errors and void formation.
Innovation Solution
Implementing a spatially-efficient interconnect structure with bridge pillars that electrically connect circuit elements across a base isolation layer, reducing die size and parasitic capacitance, and using a segmented interconnect structure to enhance electrical connections without additional manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-aspect ratio monolithic vias are used to connect circuit elements across isolation layers, then electrical connectivity is achieved, but manufacturing defects such as fill errors and void formation increase
Solution Approach 1:
The patent divides a single high-aspect-ratio via into multiple lower-aspect-ratio vias stacked vertically, with each via connected by a horizontal conductive segment. This segmentation reduces the aspect ratio of individual vias from potentially 10:1 or higher to 2:1 or 3:1, significantly improving manufacturability and reducing fill errors and voids while maintaining the same overall electrical connectivity function.
2Productivity
If transistor density is increased and device features are decreased, then device capacity and integration are improved, but manufacturing defects have larger influence on device performance
Solution Approach 1:
By segmenting interconnect paths into multiple shorter via-stacked segments, the patent reduces the impact of any single via defect on overall device performance. If one via or horizontal segment fails, alternative paths or redundancy can maintain functionality, thereby improving device performance stability despite higher transistor density.
Solution Approach 2:
The patent changes the geometric parameters of vias from high-aspect-ratio to low-aspect-ratio through segmentation, which fundamentally alters the manufacturing characteristics and defect sensitivity. This parameter change enables higher transistor density while maintaining reliability by making the interconnect structure more robust to manufacturing variations.
3Ease of manufacture
If conventional interconnect structures are used, then manufacturing processes are simple, but die size is larger and parasitic capacitance is higher
Solution Approach 1:
The patent transitions from planar interconnect routing to three-dimensional via-stacked routing with vertical and horizontal segments. This dimensional change allows signals to travel more directly between layers, reducing the horizontal routing distance and associated parasitic capacitance, while the modular via-stack structure can be integrated into existing manufacturing processes.
4Ease of manufacture
If conventional interconnect structures are used, then manufacturing processes are simple, but parasitic capacitance is higher
Solution Approach 1:
By utilizing vertical via-stacked paths combined with short horizontal segments, the patent reduces the lateral distance that signals must travel through high-capacitance interconnect regions. The three-dimensional routing approach minimizes overlapping conductors and reduces parasitic capacitance compared to conventional planar routing, while remaining compatible with standard semiconductor manufacturing processes.
Data Source
AI summary
A method of making a semiconductor device includes manufacturing a first bridge pillar; manufacturing a first transistor channel bar and first transistor source/drain electrode, the first transistor S/D electrode electrically connecting to the first bridge pillar; manufacturing a second transistor channel bar and second transistor S/D electrode; manufacturing a first metal electrode, the first bridge pillar connecting the first transistor S/D electrode and first metal electrode; manufacturing a first via connected to the first metal electrode; and manufacturing a first conductive line connected to the first via. The first transistor S/D electrode and the second transistor S/D electrode are spaced apart by a first height, the first metal electrode is separate from the second transistor S/D electrode, the first bridge pillar is separate from the second transistor S/D electrode, and the first bridge pillar has a height in the first direction substantially equal to the first height.