Bridge Router Virtual Channel Memory Bandwidth Allocation
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Solution Overview
Problem
Existing systems lack efficient control over memory access speed for peripheral devices, with different devices requiring varying access speeds, such as faster access for graphics cards, necessitating sophisticated control mechanisms.
Innovation Solution
A bridge connecting a processor unit and a peripheral device, featuring a downstream port and a router that allocates upstream channels and memory bandwidth based on identifiers stored in tables, allowing for efficient access management and resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a general-purpose DMA architecture is used to allow peripheral devices to access processor memory directly, then the load on the processor is reduced, but the access speed cannot be optimized for different types of peripheral devices
Solution Approach 1:
The downstream interface is divided into multiple virtual channels (VCs), each capable of independently accessing different regions of processor memory. This segmentation allows different peripheral devices to use different VCs with optimized access parameters, enabling high-speed access for graphics cards while maintaining standard access for other devices, thus resolving the contradiction between access speed optimization and system complexity.
Solution Approach 2:
The system dynamically allocates and configures virtual channels based on the specific requirements of each peripheral device. The bridge device can adjust memory access parameters, bandwidth allocation, and channel assignment in real-time according to device needs, allowing the system to adapt to different access speed requirements without requiring a completely different architecture for each device type.
2Productivity
If sophisticated control mechanisms are implemented to optimize access speed for different peripheral devices, then access efficiency is improved, but the system complexity increases
Solution Approach 1:
A bridge device is introduced as an intermediary between peripheral devices and the processor memory. The bridge contains the sophisticated control logic, including virtual channel management and memory access parameter configuration, isolating this complexity from both the processor and peripheral devices. This allows efficient controlled access while keeping the overall system architecture relatively simple.
Solution Approach 2:
The bridge device with its virtual channel architecture serves multiple functions: it manages memory access for different types of peripheral devices, optimizes access speed for high-performance devices like graphics cards, maintains compatibility with standard DMA operations, and provides a unified interface for diverse devices. This multi-functionality improves access efficiency across different device types without requiring separate control mechanisms for each.
Data Source
AI summary
A downstream port 22 of a bridge 20 connecting a processor unit and a peripheral device acknowledges access from the peripheral device via one of a plurality of downstream channels available for access by the peripheral device to a memory of the processor unit, the downstream channels being virtual channels provided for interfacing with the peripheral device. The router 24 routes the access to upstream channels each assigned a memory bandwidth available for access to the memory, the upstream channels being virtual channels supported by the processor unit. In this process, the router refers to a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.