Variable-Precision Floating-Point Multiplier With Bridged Carry Adders
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Solution Overview
Problem
Existing multiplier circuits in programmable logic devices (PLDs) lack the flexibility to support a wide range of intermediate floating-point precisions, limiting their functional density and efficiency in applications like machine learning.
Innovation Solution
The integration of specialized processing blocks with configurable multiplier circuitry, including carry-propagate adders, rounding circuits, and exponent handling, allows for variable precision floating-point operations, supporting formats such as FP16, FP17, FP18, and FP20, doubling functional density compared to fixed-point multiply operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional DSP blocks use fixed 18-by-19 multipliers for IEEE 754 single precision floating-point operations, then the circuit structure is simple and reliable, but the functional density is limited and cannot support a wide range of intermediate precisions
Solution Approach 1:
The multiplier circuit uses dynamic configuration through carry-propagate adders that can be selectively enabled or disabled based on the required precision. The rounding circuit dynamically adjusts its operation mode (round-to-nearest, round-toward-zero, round-toward-positive-infinity, round-toward-negative-infinity) based on control signals, allowing the same hardware to adapt to different precision requirements (FP16, FP17, FP18, FP20, FP32) without physical reconfiguration
Solution Approach 2:
The invention changes the operational parameters of the multiplier circuit by modifying the precision configuration through control signals. The carry-propagate adders can be configured to operate with different bit-widths (17-bit, 18-bit, 19-bit, 20-bit, 23-bit) by enabling or disabling specific adder stages. The rounding circuit changes its rounding mode parameter based on control inputs, allowing the same hardware structure to support multiple floating-point precision formats
2Productivity
If the multiplier circuit is configured to support multiple precision formats with configurable adders and rounding circuits, then functional density doubles compared to fixed-point operations, but the circuit complexity increases
Solution Approach 1:
The multiplier circuit is designed as a universal structure that can perform multiple functions: it supports single precision (FP32) operations, dual half-precision (FP16) operations, and intermediate precisions (FP17, FP18, FP20). The same carry-propagate adder array and rounding circuit serve all these functions by being dynamically configured through control signals, achieving multi-functionality without requiring separate dedicated circuits for each precision format
Solution Approach 2:
The carry-propagate adder array is segmented into multiple stages that can be independently controlled. The first CPA handles the most significant bits while the second CPA handles the least significant bits. This segmentation allows selective activation of adder stages to match different precision requirements, enabling the circuit to efficiently support both high-precision and low-precision operations using the same segmented structure
3Productivity
If fixed-precision multipliers are used for IEEE 754 single precision operations, then the circuit design is straightforward, but the efficiency in applications like machine learning is limited
Solution Approach 1:
The multiplier circuit employs dynamic configuration to match the computational requirements of different machine learning applications. The control logic dynamically selects the appropriate precision mode and rounding behavior based on the operational context, allowing efficient execution of both high-precision training operations and low-precision inference operations using the same hardware resource
Data Source
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AI summary
Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.