Bridged IC Architecture Using FPGA Decoding and Swappable ASICs
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Solution Overview
Problem
The complexity in ASIC design leads to potential errors and increased development costs, and since ASICs are not reprogrammable, redesigns are necessary for different applications, which can delay product shipments and increase costs.
Innovation Solution
A system comprising a Field-Programmable Gate Array (FPGA) and an Application-Specific Integrated Circuit (ASIC) on the same circuit board, where the FPGA decodes instructions and transmits them to the ASIC for execution, allowing the ASIC to be swapped for different designs or applications, reducing design complexity and enabling deterministic execution of instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ASIC design complexity is increased to handle more functions, then functionality is improved, but design errors and development costs increase
Solution Approach 1:
The system divides functionality into two separate chips: an FPGA chip that handles instruction decoding and a control chip that executes instructions. This segmentation allows each chip to specialize in specific functions, improving overall reliability while maintaining versatility.
Solution Approach 2:
The patent introduces an intermediary instruction set architecture (ISA) that mediates between the FPGA and the control chip. The ISA layer allows the control chip to be swapped for different applications without redesigning the entire system, reducing design errors while maintaining adaptability.
2Adaptability or versatility
If ASIC is redesigned for different applications, then adaptability is improved, but product shipment delays and development costs increase
Solution Approach 1:
The system makes the control chip dynamically replaceable through standardized interfaces and instruction sets. Different control chips can be swapped to support different applications without redesigning the entire system, enabling rapid adaptation while avoiding shipment delays.
Solution Approach 2:
The patent creates a universal instruction set architecture that can be implemented across different control chips. This universal ISA allows a single FPGA design to work with multiple different control chips for different applications, improving adaptability without requiring redesigns.
3Device complexity
If all processing is done on a single chip, then integration is improved, but communication tasks bottleneck performance
Solution Approach 1:
The system segments processing tasks between the FPGA chip (instruction decoding) and the control chip (execution). This segmentation eliminates the bottleneck by allowing parallel processing of instruction decoding and execution, improving overall productivity while maintaining reasonable integration through standardized interfaces.
Data Source
AI summary
Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.