Bridged Class-D RF Amplifier Layout for Low-Parasitic Switching
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Solution Overview
Problem
Parasitic inductances and resistances in the connections between driver devices and power switching devices in Class D amplifiers limit the maximum frequency of the analog output signal, restricting the frequency at which power switching devices can be switched.
Innovation Solution
The implementation of a full-bridge Class-D RF amplifier circuit with high bandgap semiconductor power devices, such as SiC MOSFETs, and the use of driver devices adjacent to switching devices with Kelvin source connections to minimize parasitic inductances and resistances, allowing for direct low-inductance return paths and reduced source inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If driver devices are connected to power switching devices through conventional connections, then the circuit is easier to manufacture, but parasitic inductances and resistances increase, limiting the maximum switching frequency
Solution Approach 1:
The patent positions driver devices in a planar arrangement adjacent to power switching devices, utilizing spatial dimensionality to minimize connection path length. This dimensional optimization reduces parasitic inductance by creating direct, short connections between driver output terminals and power device control terminals, enabling higher switching frequencies while maintaining manufacturability through standardized PCB layouts.
Solution Approach 2:
The patent extracts and minimizes the parasitic inductance and resistance by creating separate, dedicated connection paths for each driver-power device pair. By isolating these critical signal paths from other circuit elements and using direct adjacent positioning, the harmful parasitic effects are effectively removed from the signal path, allowing the circuit to achieve higher operating frequencies.
2Reliability
If driver devices are positioned away from power switching devices for easier assembly, then manufacturing is simpler, but parasitic inductances increase, reducing signal integrity at high frequencies
Solution Approach 1:
The patent merges the driver devices and power switching devices into a single integrated module where driver devices are positioned directly adjacent to their corresponding power switching devices. This merging eliminates the need for long interconnecting traces and reduces assembly complexity by treating the driver-power device pair as a functional unit, thereby maintaining signal integrity while simplifying the overall manufacturing process.
3Loss of energy
If conventional connection layouts are used, then the circuit board design is simpler, but parasitic resistances increase, reducing power efficiency and increasing heat generation
Solution Approach 1:
The patent applies local quality optimization by creating low-resistance connection paths specifically at the driver-power device interface, while other parts of the circuit can use conventional layouts. This localized optimization reduces parasitic resistance where it matters most (in the high-frequency control signals), improving power efficiency and reducing heat generation without requiring complete redesign of the entire circuit board.
Data Source
AI summary
A full-bridge class-D amplifier circuit comprises first through fourth power devices. First conduction terminals of the first and third power devices are coupled to a first power supply voltage, and second conduction terminals of the second and fourth power devices are coupled to a second power supply voltage. A second conduction terminal of the first power device and a first conduction terminal of the second power device are coupled to a first amplifier output. A second conduction terminal of the third power device and a first conduction terminal of the fourth power device are coupled to a second amplifier output. Left and right driver devices respectively disposed adjacent to left and right sides of the first power device have outputs respectively coupled to left and right control terminals respectively disposed on the left and right sides of the first power device.