Bridged SAR ADC Capacitor Bank for Fine Gain Calibration
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face challenges with high power consumption, silicon area requirements, and complexity due to binary-weighted capacitor banks, which also necessitate precise matching and correction for gain and offset mismatches, especially in successive-approximation (SAR) ADCs used as sub-ADCs, where finer gain control is needed but difficult to achieve accurately.
Innovation Solution
The implementation of a bridged capacitor bank with additional capacitors, including a capacitor ladder and switch networks, allows for finer gain control and compensation of matching errors, using a pseudo-random binary sequence for calibration and bridge ratio estimation, enabling more accurate and efficient SAR ADC operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a binary-weighted capacitor bank is used in a SAR ADC, then the ADC can achieve high sampling rates, but the power consumption and silicon area increase exponentially with the number of bits
Solution Approach 1:
The capacitor bank is divided into two separate banks: a main capacitor bank and a sub capacitor bank. The main bank handles the most significant bits while the sub bank handles the least significant bits. This segmentation allows each bank to use smaller capacitors, reducing the exponential growth of power consumption and area with bit depth.
Solution Approach 2:
The patent introduces a bridge capacitor that connects the two capacitor banks, adding a new dimensional relationship between them. This bridge capacitor enables the sub capacitor bank to contribute to the overall DAC output in a controlled manner, allowing fine gain control without requiring exponentially larger capacitors.
2Speed
If a binary-weighted capacitor bank is used in a SAR ADC, then the ADC can achieve high sampling rates, but the silicon area increases exponentially with the number of bits
Solution Approach 1:
The capacitor bank is divided into two separate banks: a main capacitor bank and a sub capacitor bank. The main bank handles the most significant bits while the sub bank handles the least significant bits. This segmentation allows each bank to use smaller capacitors, reducing the exponential growth of power consumption and area with bit depth.
Solution Approach 2:
The patent introduces a bridge capacitor that connects the two capacitor banks, adding a new dimensional relationship between them. This bridge capacitor enables the sub capacitor bank to contribute to the overall DAC output in a controlled manner, allowing fine gain control without requiring exponentially larger capacitors.
3Measurement precision
If additional capacitors are added to a bridged capacitor bank for finer gain control, then gain control precision improves, but device complexity increases
Solution Approach 1:
The capacitor bank is divided into two separate banks: a main capacitor bank and a sub capacitor bank. The main bank handles the most significant bits while the sub bank handles the least significant bits. This segmentation allows each bank to use smaller capacitors, reducing the exponential growth of power consumption and area with bit depth.
Solution Approach 2:
The patent introduces a bridge capacitor that connects the two capacitor banks, adding a new dimensional relationship between them. This bridge capacitor enables the sub capacitor bank to contribute to the overall DAC output in a controlled manner, allowing fine gain control without requiring exponentially larger capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and silicon area requirements while providing precise gain control and accurate calibration, enhancing the linearity and efficiency of SAR ADCs in time-interleaved systems.
Implementation Method 1
A SAR ADC comprises a capacitor bank configured to control a gain of the SAR ADC, wherein the capacitor bank comprises a first capacitor network comprising a plurality of capacitors
Data Source
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AI summary
Disclosed is a SAR (Ai) comprising an input for receiving an input voltage (Vin), a comparator (100), a first switch network (120) configured to be controlled by the SAR state machine (110) and connected to the input of the SAR ADC (Ai) and to reference voltage nodes, and a first capacitor network (130). The first capacitor network (130) comprises a first node (140) connected to an input of the comparator (100), a second node (150), and a bridge capacitor (Cb) connected between the first node (140) and the second node (150). Furthermore, the first capacitor network (130) comprises a first set (160) of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the first set is connected to the first node (140) and the second terminal of each capacitor in the first set is connected to the switch network (120). Moreover, the first capacitor network (130) comprises a second set (170) of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the second set is connected to the second node (150) and the second terminal of each capacitor in the first set is connected to the switch network (120). The SAR ADC (Ai) further comprises a second capacitor network (180) connected to the second node (150) of the first capacitor network and configured to control a gain of the SAR ADC (Ai).