Bridged SAR ADC Capacitor Network for Gain and Bridge Ratio Correction
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face challenges with high matching requirements between sub-ADCs for time, offset, and gain, leading to power and silicon area consumption issues, especially when using binary-weighted capacitor banks, which become complex and inefficient for large bit sizes.
Innovation Solution
The implementation of bridged capacitor banks with additional capacitors to compensate for gain errors and bridge-ratio inaccuracies, allowing for finer gain control and improved matching through a capacitor ladder structure and test sequence injection for bridge ratio estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a binary-weighted capacitor bank is used in a SAR ADC, then the ADC can achieve high sampling rates, but the power consumption and silicon area increase exponentially with the number of bits
Solution Approach 1:
The capacitor bank is divided into two separate sections: a main DAC (MDAC) with most significant bits and a sub-DAC (SDAC) with least significant bits. This segmentation allows each section to use smaller capacitors, reducing the exponential growth of power consumption and area with bit depth while maintaining the required sampling rate performance
2Speed
If a binary-weighted capacitor bank is used in a SAR ADC, then the ADC can achieve high sampling rates, but the silicon area increases exponentially with the number of bits
Solution Approach 1:
The capacitor bank is divided into two separate sections: a main DAC (MDAC) with most significant bits and a sub-DAC (SDAC) with least significant bits. This segmentation allows each section to use smaller capacitors, reducing the exponential growth of power consumption and area with bit depth while maintaining the required sampling rate performance
Solution Approach 2:
The sub-DAC is effectively nested within the overall DAC structure, with the SDAC capacitors being much smaller and positioned to interface with the MDAC through a bridge capacitor. This nested arrangement optimizes the use of silicon area by placing smaller components in a hierarchical structure
3Speed
If a binary-weighted capacitor bank is used in a SAR ADC, then the ADC can achieve high sampling rates, but the circuit complexity and layout difficulty increase due to matching requirements
Solution Approach 1:
The capacitor bank is divided into two separate sections: a main DAC (MDAC) with most significant bits and a sub-DAC (SDAC) with least significant bits. This segmentation allows each section to use smaller capacitors, reducing the exponential growth of power consumption and area with bit depth while maintaining the required sampling rate performance
Solution Approach 2:
A bridge capacitor is introduced as an intermediary element connecting the MDAC and SDAC sections. This bridge capacitor serves as a mediator that enables the two separate capacitor banks to work together as a unified DAC structure, simplifying the overall circuit architecture and reducing layout complexity
4Manufacturing precision
If the bridge ratio in a bridged capacitor bank differs from the ideal value, then the overall DAC transfer becomes nonlinear, but achieving accurate bridge ratio matching is difficult due to parasitics and manufacturing variations
Solution Approach 1:
A test sequence is injected into the DAC and the output is analyzed to estimate the actual bridge ratio. This feedback mechanism allows the system to measure the real bridge ratio including parasitic effects, and this estimated value is then used to correct the digital output code, ensuring accurate DAC transfer characteristics despite manufacturing variations
Solution Approach 2:
The digital output code is dynamically adjusted based on the estimated bridge ratio. By changing the code parameters according to the measured bridge ratio, the system compensates for deviations from ideal values and maintains accurate DAC transfer linearity across different operating conditions
Data Source
AI summary
Disclosed is a SAR ADC (Ai) having an input for receiving an input voltage, a comparator, a first switch network configured to be controlled by the SAR state machine and connected to the input of the SAR ADC and to reference voltage nodes, and a first capacitor network. The first capacitor network has a first node connected to an input of the comparator, a second node, and a bridge capacitor (Cb) connected between the first node and the second node. Furthermore, the first capacitor network comprises a first set of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the first set is connected to the first node and the second terminal of each capacitor in the first set is connected to the switch network. Moreover, the first capacitor network comprises a second set of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the second set is connected to the second node and the second terminal of each capacitor in the first set is connected to the switch network. The SAR ADC further comprises a second capacitor network configured to control a gain of the SAR ADC.