Bridging Contact Structure for Cap-Less GAA Gate Contacts
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Solution Overview
Problem
The integration of multi-gate devices in semiconductor manufacturing is challenging due to complexity and the need for improved gate control and reduced short-channel effects.
Innovation Solution
A semiconductor structure is fabricated using a gate-all-around (GAA) transistor design, where the gate structure is formed directly on the gate structure without a cap layer, and a bridging contact structure is formed to connect the source/drain and gate contacts, enhancing the quality of the gate contact and facilitating efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a cap layer is used to form the gate contact structure, then the manufacturing process is more straightforward, but the gate contact quality deteriorates due to interface defects
Solution Approach 1:
The patent removes the cap layer from the gate contact formation process. By directly forming the gate contact structure on the gate electrode without an intervening cap layer, the interface defects between the cap layer and gate electrode are eliminated, thereby improving gate contact quality while maintaining process feasibility
Solution Approach 2:
The gate contact structure is formed directly on the gate electrode during the initial formation stage, before subsequent dielectric layers are deposited. This preliminary action ensures optimal gate contact quality is established early in the process, avoiding the need for later modifications or additional cap layer steps
2Reliability
If multi-gate devices are integrated to improve gate control, then device performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The gate structure is divided into multiple segments wrapping around the channel from different directions (front gate, back gate, and sidewall gates). This segmentation enables independent control of each gate region, improving overall gate control and allowing separate optimization of different device regions while maintaining manufacturability through modular fabrication steps
Solution Approach 2:
The gate control is extended from a traditional planar two-dimensional configuration to a three-dimensional multi-gate structure that wraps around the channel. This dimensional transition increases the gate-channel interface area and improves electrostatic control, while the systematic fabrication approach manages the increased structural complexity
3Manufacturing precision
If the gate contact structure is formed directly on the gate electrode, then gate contact quality improves, but the process integration becomes more challenging
Solution Approach 1:
The formation of the gate contact structure is merged with the gate electrode formation process itself. By combining these two steps into a single integrated process where the gate contact is formed concurrently with the gate electrode, the patent achieves high gate contact quality while reducing the total number of process steps and simplifying process integration
Data Source
AI summary
Semiconductor structures and methods for manufacturing the same are provided. The method includes a gate structure formed over a substrate. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure, and a contact etch stop layer (CESL) disposed over the S/D structure. The semiconductor structure includes a dielectric layer disposed over the CESL. The semiconductor structure includes an S/D contact structure extending through the dielectric layer to electrically couple to the S/D structure. The semiconductor structure includes a gate contact structure formed through the dielectric layer and landing on the gate structure, and the gate contact structure is in direct contact with the gate structure. The semiconductor structure includes a bridging contact structure covering the gate contact structure and the S/D contact structure, and a bottommost surface of the bridging contact structure interfaces a topmost surface of the S/D contact structure.