Embedded Bridging Layer Packaging for Dense Chip Interconnection

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Solution Overview

Problem

Existing semiconductor packaging technologies require high-cost, thick TSV/TGV intermediate layers for chip interconnection, limiting miniaturization and integration, and offering low design freedom and integration degree.

Innovation Solution

A packaging structure comprising a core layer, bridging layer, dielectric layers, and bonding pad layers with vias for chip interconnection, allowing for high-density integration and reduced manufacturing costs by embedding the bridging layer in the dielectric layer and connecting chips through the bonding pad layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a TSV/TGV intermediate layer is used for chip interconnection, then chip interconnection is realized, but the packaging module volume increases and manufacturing cost increases

Engineering Contradiction:

Improvechip interconnectionVSAvoidpackaging module volume

Core Design Contradiction:

ReliabilityVSVolume of stationary object

Solution Approach 1:

The patent extracts and eliminates the TSV/TGV intermediate layer from the packaging structure. By directly connecting chips to the substrate through solder balls, the thick intermediate layer is removed, significantly reducing the packaging module volume while maintaining chip interconnection functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the chip mounting function and the interconnection function into a single integrated structure. The substrate directly provides both mechanical support for chip mounting and electrical interconnection pathways, eliminating the need for a separate intermediate layer.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If a TSV/TGV intermediate layer is used for chip interconnection, then chip interconnection is realized, but manufacturing cost increases

Engineering Contradiction:

Improvechip interconnectionVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent removes the complex and expensive TSV/TGV intermediate layer manufacturing process. By using a simpler direct-soldering approach, the manufacturing steps are reduced, equipment requirements are lowered, and overall production cost is decreased.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the expensive, complex TSV/TGV intermediate layer with a simpler, more cost-effective substrate-based interconnection structure that uses standard soldering materials and processes, significantly reducing material and manufacturing costs.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Reliability

If a TSV/TGV intermediate layer is used for chip interconnection, then multi-chip interconnection is realized, but the degree of freedom in design is limited

Engineering Contradiction:

Improvemulti-chip interconnectionVSAvoiddesign freedom

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal substrate structure that can accommodate multiple chips with different configurations. The substrate's circuit patterns and solder ball arrangements can be flexibly designed to support various interconnection topologies, enabling greater design freedom for multi-chip packages.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces flexible design elements that allow the interconnection structure to adapt to different chip arrangements and configurations. The circuit pathways and connection points can be dynamically configured based on specific application requirements, enhancing design versatility.

Inventive Principle:

Principle #15Dynamics

4Reliability

If a TSV/TGV intermediate layer is used for chip interconnection, then chip interconnection is realized, but the integration degree is low

Engineering Contradiction:

Improvechip interconnectionVSAvoidintegration degree

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the chip mounting function and electrical interconnection function into a single integrated substrate structure. This merging eliminates the need for separate intermediate layers and reduces the overall number of components, thereby increasing the integration degree of the packaging module.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20240021525A1Packaging structure for realizing chip interconnection and manufacturing method thereof

Publication Date: 2024.01.18 ZHUHAI YUEXIN SEMICON LLC

AI summary

A packaging structure for realizing chip interconnection includes a core layer, a bridging layer, a first dielectric layer, a second dielectric layer, a first bonding pad layer and a second bonding pad layer. The first dielectric layer is arranged between the core layer and the first bonding pad layer, the second dielectric layer is arranged between the second bonding pad layer and the core layer. The first bonding pad layer is connected with the core layer through a first via, the second bonding pad layer is connected with the core layer through a second via. The bridging layer is embedded in the first dielectric layer. The bridging layer is electrically insulated from the core layer, and the bridging layer is connected with the first bonding pad layer through a third via.