Brittle Guard Ring for Semiconductor Stress Management

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Solution Overview

Problem

The die sawing process in semiconductor chip fabrication generates stresses that can cause cracks and degrade the reliability of integrated circuits, as these stresses are transmitted from the scribe lane region to the main chip region during cutting.

Innovation Solution

Incorporating a guard ring with higher brittleness than the insulating layer in the scribe lane region, which can be an insulating or conductive guard ring, to absorb and dissipate the stress, thereby preventing its transmission to the main chip region, and reducing the scribe lane width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the die sawing process is performed to cut the scribe lane region, then the semiconductor chips are physically separated, but stresses are generated and transmitted to the main chip region causing cracks

Engineering Contradiction:
Improvechip separationVSAvoidintegrated circuit reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A guard ring structure is introduced as an intermediary element between the scribe lane region and the main chip region. This guard ring absorbs and blocks the stress waves generated during die sawing, preventing them from reaching the integrated circuits in the main chip region, thus protecting the circuits from stress-induced cracks while allowing the scribe lane to be successfully cut

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The guard ring is formed in advance during the fabrication process, before the die sawing operation. It serves as a pre-positioned stress-absorbing structure that cushions the main chip region against the harmful stresses that will be generated during the subsequent cutting process, thereby preventing damage before it occurs

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Productivity

If the scribe lane region width is reduced to increase chip density, then more chips can be produced per substrate, but stress concentration during die sawing increases

Engineering Contradiction:
Improvechip densityVSAvoidstress concentration
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The guard ring structure is selectively positioned at the boundary between the scribe lane region and the main chip region, where stress concentration occurs during die sawing. By localizing the stress-absorbing function to this critical area, the design allows for reduced scribe lane width and increased chip density while still providing adequate stress protection through the strategically placed guard ring

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The guard ring effectively alleviates stress during the die sawing process, reducing the likelihood of cracks in the main chip region and enhancing the reliability of integrated circuits, while also minimizing the scribe lane width to increase chip density.

Implementation Method 1

The guard ring has a brittleness greater than a brittleness of the insulating layer... the guard ring effectively alleviates stress during the die sawing process, reducing the likelihood of cracks in the main chip region

Methodology Applied
Scientific EffectStress absorption and dissipation: Stress Relaxation

Data Source

PatentUS8623743B2Semiconductor chips having guard rings and methods of fabricating the same
Publication Date: 2014.01.07 SAMSUNG ELECTRONICS CO LTD
  • US8623743B2 patent drawing
  • US8623743B2 patent drawing
  • US8623743B2 patent drawing

AI summary

Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.