Broadband Frequency Tripler Using Harmonic Mixing and Filtering
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Solution Overview
Problem
Existing broadband frequency triplers, whether diode-based or transistor-based, face challenges with high conversion loss, narrow bandwidth, and high power consumption, necessitating the development of a more efficient frequency multiplier with improved performance in terms of conversion gain, bandwidth, and power efficiency.
Innovation Solution
A four-stage frequency multiplier using transistors, comprising a harmonic generator, a passive filter, a mixer, and an attenuator, where the filter's frequency response manipulates harmonic signal powers to ensure a flat output power for the 3rd order harmonic signal across a wide frequency range, and coupled transmission lines suppress undesired harmonics, achieving a wide bandwidth and low input power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a frequency tripler is built by diodes to achieve broadband operation, then the bandwidth is wide (80-110 GHz), but the conversion loss is large (around 20 dB) and input power requirement is high (15 dBm)
Solution Approach 1:
The frequency tripler is divided into two independent stages: a first stage for frequency multiplication and a second stage for harmonic filtering. This segmentation allows each stage to be optimized independently - the first stage uses diodes for broadband operation while the second stage compensates for conversion loss, resolving the contradiction between wide bandwidth and low conversion loss
Solution Approach 2:
An intermediate filter is introduced between the first and second stages to selectively pass the desired third harmonic while blocking other harmonics. This intermediary component enables the system to maintain wide bandwidth by allowing selective frequency transmission, while the second stage can then operate with optimized power levels
2Loss of energy
If a frequency tripler is built by transistors to achieve positive conversion gain, then the conversion gain is positive (up to 7 dB) and input power is low (3 dBm), but the bandwidth is narrow (16 GHz: 119-135 GHz)
Solution Approach 1:
The system is segmented into two stages where the first stage (transistor-based) provides positive conversion gain and low input power operation, while the second stage (diode-based with filter) extends the bandwidth. This segmentation allows each stage to specialize - the transistor stage optimizes for gain while the filter stage optimizes for bandwidth
Solution Approach 2:
The invention merges the advantages of both transistor-based (positive conversion gain, low input power) and diode-based (wide bandwidth) frequency triplers into a single two-stage system, combining their strengths to achieve both good conversion gain and wide bandwidth simultaneously
3Power
If additional power amplifiers are added at output and input to boost power, then the output and input power are increased, but the DC power consumption increases significantly
Solution Approach 1:
The frequency tripler design achieves sufficient output power through optimized harmonic generation and filtering in the two-stage configuration, without requiring additional power amplifiers. The system serves its own power needs through efficient frequency multiplication, reducing DC power consumption while maintaining adequate output power levels
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves 0 dB conversion gain with an input power of 5 dBm, offering a similar frequency bandwidth with high conversion gain and low power consumption, significantly improving upon existing diode triplers in terms of efficiency and bandwidth.
Implementation Method 1
a passive filter, wherein a frequency response of the passive filter has either a peak or a dip at an upper frequency end of a frequency range of the input signal such that at output of the second stage, either a power of the 1st order harmonic signal decrease and a power of the 2nd order harmonic signal increases when the input signal frequency increases
Implementation Method 2
a third stage configured to mix the 1st and the 2nd order harmonics signals received from the second stage to generate 3rd order harmonic signals
Implementation Method 3
a fourth stage configured to supress the 1st and even-order harmonics signals and output a signal dominated with a frequency 3 times of the input signal frequency
Data Source
Figure 1~2
Figure 3(a)~3(c)
Figure 4(a)~4(b)
AI summary
A frequency multiplier (200) generates an output signal with a frequency 3 times of the input signal frequency. The frequency multiplier (200) comprises four cascaded stages. A first stage (201) is configured to receive an input signal and generate harmonics signals of the input signal. A second stage (202) is a passive filter, a frequency response of the passive filter has either a peak or a dip around an upper frequency end of a frequency band of the input signal. A third stage (203) is configured to mix the 1st and the 2nd order harmonics signals to generate 3rd order harmonic signals. A fourth stage (204) is configured to supress the 1st and even-order harmonics signals and output a signal dominated with a frequency 3 times of the input signal frequency.