Broadcast Memory Subsystem for Parallel Processor Bandwidth
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Solution Overview
Problem
Existing processor systems face limitations in data-transfer bandwidth during the execution of scheduled parallel processes, leading to inefficiencies in power consumption and processing time, particularly in edge computing environments where cloud-based resources may not be available.
Innovation Solution
A processor system with a broadcast subsystem that includes a direct memory access core, a set of primary memory units, and a broadcast scheduler, enabling simultaneous data transfer to multiple memory units via broadcast buses, combined with a memory management subsystem that reduces power consumption by selectively transitioning inactive memory modules to a low-power state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory access methods are used in processor systems, then system simplicity is maintained, but data-transfer bandwidth is limited and processing time increases
Solution Approach 1:
The memory system is segmented into multiple primary memory units (L1 cache banks) that can be accessed independently and simultaneously. Each memory unit has dedicated access ports, allowing parallel data transfer operations to occur without contending for a single shared resource, thereby increasing data-transfer bandwidth and reducing processing time.
Solution Approach 2:
The patent introduces a dimensional expansion in the memory access architecture by adding multiple independent access ports (read ports and write ports) to each memory unit. This multi-dimensional access structure allows simultaneous operations across different ports, transforming a single-threaded sequential access model into a parallel multi-threaded access model, thus dramatically improving bandwidth.
2Productivity
If more memory access ports are added to increase bandwidth, then data-transfer capability improves, but device complexity increases
Solution Approach 1:
The arbitration logic is extracted and distributed to individual memory units rather than being centralized. Each memory unit contains its own arbitration mechanism to manage its dedicated ports independently, eliminating the need for a complex centralized arbiter that would coordinate all ports across all memory units, thus reducing overall system complexity while maintaining high bandwidth.
Solution Approach 2:
Each memory unit is designed with universal functionality to handle multiple types of operations (reads, writes, read-modify-write) through its dedicated ports. This modular universal design allows the same memory unit structure to be replicated across the system, simplifying the overall architecture by avoiding the need for different specialized structures for different operations.
3Speed
If all memory modules remain active to ensure fast access, then access speed is maintained, but power consumption increases
Solution Approach 1:
The system performs preliminary actions by predicting which memory units will be needed soon based on access patterns, and proactively keeping those units in active state. Meanwhile, memory units that are not predicted to be needed can be transitioned to low-power states in advance, ensuring that when access is required, the data is already available or can be quickly retrieved, thus maintaining speed while reducing power consumption.
Solution Approach 2:
The patent dynamically changes the operational state parameter of memory modules between active and low-power modes based on real-time or predicted access requirements. This parameter switching allows the system to adapt power consumption levels to actual workload demands, maintaining fast access when needed while conserving energy during idle or low-demand periods.
Data Source
AI summary
A broadcast subsystem of a processor system includes: a set of broadcast buses, each broadcast bus in the set of broadcast buses electrically coupled to a subset of primary memory units in the set of primary memory units; a primary memory unit queue: configured to store a first set of data transfer requests associated with the set of primary memory units; electrically coupled to the data buffer a broadcast scheduler: electrically coupled to the primary memory unit queue; electrically coupled to the set of broadcast buses; and configured to transfer source data from the data buffer to a target subset of primary memory units in the set of primary memory units via the set of broadcast buses based on the set of data transfer requests stored in the primary memory unit queue.