Broadcast Parallel Processing Unit for Memory Bandwidth Bottleneck

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Solution Overview

Problem

Conventional processing units face limitations due to the von Neumann bottleneck, where memory bandwidth restricts computational performance, and existing solutions like GRAPE, reconfigurable computers, and SIMD massively parallel computers lack versatility, have limitations in integration and operational speed, especially for double-precision floating-point operations.

Innovation Solution

A processing unit with multiple element processors, each having a logic unit, arithmetic unit, and register file, connected via a shared memory port, allowing for parallel computation with different parameter data and shared instruction execution, which increases computational speed without memory bandwidth constraints, using 72-bit floating-point data and various instruction modes for efficient arithmetic and logic operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processor units are integrated into a single chip to increase computational speed, then processing performance improves, but memory bandwidth becomes insufficient and von Neumann bottleneck limitations occur

Engineering Contradiction:

Improvecomputational speedVSAvoidmemory bandwidth

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The system segments memory resources by providing each element processor with a dedicated local memory unit, eliminating the shared memory bottleneck. This segmentation allows each processor to access its own memory independently, preventing memory bandwidth limitations from constraining multiple parallel processors.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The architecture implements a hierarchical memory structure where local memory units are nested within each element processor, and these processors are further integrated into a larger array. This nested configuration allows fast local access while enabling parallel operations across multiple processors without contending for the same memory bandwidth.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Productivity

If dedicated computing units are used to achieve high computational speed, then processing performance improves, but versatility is reduced as computations are specified at hardware implementation stage

Engineering Contradiction:

Improvecomputational speedVSAvoidcomputation flexibility

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

Each element processor is designed as a universal computing unit capable of executing various operations including addition, subtraction, multiplication, division, and logical operations. The processors can handle different data types (single-precision and double-precision floating-point) and perform both vector and matrix operations, providing versatility while maintaining high-speed parallel processing capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system employs a control processor that dynamically configures and manages the element processors through programmable instructions. This dynamic control allows the same hardware architecture to adapt to different computational tasks and algorithms, combining the speed of dedicated hardware with the flexibility of software programming.

Inventive Principle:

Principle #15Dynamics

3Adaptability or versatility

If reconfigurable computers with FPGAs are used to improve versatility, then computation flexibility improves, but circuit scale is limited and operating speed cannot be increased

Engineering Contradiction:

Improvecomputation flexibilityVSAvoidoperating speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The invention replaces the reconfigurable FPGA architecture with a fixed but highly integrated processor array design. By substituting the mechanical reconfiguration capability with a optimized static architecture featuring dedicated arithmetic units and local memory, the system achieves significantly higher operating speeds while maintaining versatility through software-controlled operation modes and instruction sets.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Adaptability or versatility

If FPGAs are designed to be reconfigurable to improve versatility, then computation flexibility improves, but computing speed for double-precision floating-point operations decreases

Engineering Contradiction:

Improvecomputation flexibilityVSAvoiddouble-precision computing speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The element processors are equipped with specialized arithmetic units optimized for double-precision floating-point operations. Each processor contains dedicated adders, subtractors, multipliers, and dividers with appropriate precision, ensuring high-speed double-precision computation. This local optimization of computational quality in each processor unit maintains versatility while achieving the required computing speed for demanding numerical applications.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7558943B2Processing unit for broadcast parallel processing

Publication Date: 2009.07.07 MAKINO JUN ICHIRO

AI summary

A processing unit includes a control processor and a plurality of element processors having register files. At least two of the element processors pre-receive different parameters, store the parameter data in the register files, receive the same memory address and the same instruction broadcast by the control processor, read the same data from the external memory via a memory port based on the memory address, and perform at least one of logic computation and arithmetic computation for the same data in accordance with the same instruction and based on the different parameters.