Broadcast Scan Network Circuit Mode Switching

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Solution Overview

Problem

Daisy chained Joint Test Action Group (JTAG) registers result in long read/write times due to the need to shift test data across multiple registers, and existing broadcast network designs lack flexibility in switching between scan modes and managing test data distribution efficiently.

Innovation Solution

A new test scan network circuit that supports both broadcast and daisy scan modes, with an improved segment insertion bit lock/unlock feature and option to force reset shift cells, enabling selective bypass of test partitions and clusters, and is compliant with the IEEE 1687 standard, reducing the time required to switch between modes and improving test efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If daisy chained JTAG registers are used, then test data can be distributed across multiple registers, but read/write times become long due to sequential shifting requirements

Engineering Contradiction:
Improvetest data distribution efficiencyVSAvoidread/write time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The scan network circuit dynamically switches between broadcast mode and daisy mode based on test requirements. In broadcast mode, test data is simultaneously distributed to multiple JTAG registers, eliminating the sequential shifting requirement and reducing read/write time while maintaining efficient test data distribution capability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The scan network is divided into multiple independent JTAG register instances that can be individually configured. Each register can be selectively activated or bypassed using segment insertion bits, allowing flexible test data distribution to specific segments without requiring sequential shifting through the entire chain

Inventive Principle:
Principle #1Segmentation

2Productivity

If broadcast mode is used for all scan segments, then test data distribution is efficient, but flexibility to bypass specific partitions or switch to daisy mode is reduced

Engineering Contradiction:
Improvetest data distribution efficiencyVSAvoidmode switching flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

Each JTAG register instance includes a segment insertion bit that can be dynamically configured between broadcast mode and daisy mode. This allows selective activation of broadcast functionality for specific partitions while maintaining the ability to switch to daisy mode for others, providing both efficient test data distribution and flexible adaptability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The scan network is segmented into multiple independently controllable JTAG register instances, each with its own segment insertion bit. This segmentation enables selective bypass of specific partitions or clusters by setting their corresponding segment insertion bits, while maintaining broadcast mode for other segments, thus achieving both efficiency and flexibility

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If segment insertion bit lock/unlock feature is added, then switching between broadcast and daisy modes is enabled, but circuit complexity increases

Engineering Contradiction:
Improvemode switching capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The segment insertion bit serves multiple functions: it controls the bypass/activate state of individual JTAG registers, enables mode switching between broadcast and daisy, and provides lock/unlock functionality for configuration stability. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10436840B2Broadcast scan network
Publication Date: 2019.10.08 NVIDIA CORP
  • US10436840B2 patent drawing
  • US10436840B2 patent drawing
  • US10436840B2 patent drawing

AI summary

A distributed test circuit includes partitions arranged in series to form a scan path, each partition including a scan multiplexer, a test data register, and a segment insertion bit component. The scan multiplexer of each partition provides inputs to the corresponding test data register of the each partition. Broadcast control logic generates a select signal to the scan multiplexer of each partition to place the test circuit in a broadcast mode when the select signal is asserted, and to switch the test circuit to a daisy mode when select signal is de-asserted. The segment insertion bit is operable to include or bypass each partition from the scan path.