Broadside RAM for Low-Cycle Data Transfer in Industrial Ethernet
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Solution Overview
Problem
Existing industrial control systems, such as those using SoCs, DSPs, and FPGAs, face challenges in achieving fast task switching and multi-protocol flexibility for real-time communication, particularly in industrial Ethernet applications, with conventional systems being inadequate in speed and flexibility.
Innovation Solution
The integration of a broadside random-access memory (BS-RAM) component that allows for the loading and retrieval of 32 bytes of data in three clock cycles, enabling fast data transfer and parallel mathematical operations, along with hardware accelerators and a hybrid architecture that supports gigabit Ethernet communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional memory access methods are used, then system flexibility is maintained, but data transfer speed and latency are insufficient for real-time industrial Ethernet communication
Solution Approach 1:
The memory system is segmented into broadside RAM and conventional RAM, with the broadside RAM specifically optimized for high-speed access patterns required by industrial Ethernet protocols. This segmentation allows the system to achieve high data transfer speeds for time-critical operations while maintaining conventional memory for other purposes.
Solution Approach 2:
The broadside RAM is pre-configured with direct mapping to processor registers, eliminating the need for complex address translation and control logic during runtime. This preliminary setup enables immediate high-speed access without adding operational complexity.
2Productivity
If fast task switching is implemented, then real-time communication performance improves, but system complexity increases
Solution Approach 1:
The broadside RAM is merged directly with the processor register file, creating a unified high-speed storage structure. This integration eliminates the need for separate memory controllers and address logic, achieving fast task switching without proportionally increasing system complexity.
Solution Approach 2:
The broadside RAM serves multiple functions: it acts as both register file and memory storage, and supports both high-speed data transfer and protocol-specific operations. This multi-functionality reduces the need for separate specialized components.
3Speed
If 32 bytes of data are stored and retrieved in three clock cycles, then data transfer speed increases, but memory access overhead increases
Solution Approach 1:
The broadside RAM provides locally optimized access characteristics specifically for 32-byte data units, which is the standard transfer size for industrial Ethernet protocols. This local optimization achieves high retrieval speed for the specific access pattern while minimizing overhead for that operation.
Solution Approach 2:
The memory system changes its operational parameters based on access type: for broadside accesses, it uses a 3-clock cycle optimized path, while for other accesses it uses conventional timing. This parameter adaptation allows high speed for critical operations without incurring overhead for all memory operations.
4Productivity
If parallel mathematical operations are performed on data during store operations, then processing efficiency improves, but hardware complexity increases
Solution Approach 1:
Mathematical operations are performed continuously on data during the store operation itself, rather than in separate processing steps. This continuity allows the same hardware circuit to perform both storage and computation functions simultaneously, improving efficiency without proportionally increasing complexity.
Solution Approach 2:
The broadside RAM circuit performs mathematical operations on data automatically during store operations without requiring separate control logic or additional processing stages. The memory write circuit itself provides the computational function, reducing overall hardware complexity.
Data Source
AI summary
A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.