Backside Illuminated Image Sensor With 3D Transistor Structure
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Solution Overview
Problem
Existing image sensors face challenges in reducing chip area and improving image quality due to the limitations of planar transistor structures, which lead to increased dark current, noise, and parasitic capacitance, making it difficult to further miniaturize pixels while maintaining performance.
Innovation Solution
A backside illuminated image sensor with a three-dimensional transistor structure is developed, where source follower and reset transistors are formed as protruding structures with insulating sidewalls and grooves, allowing for a gate to be isolated and reducing parasitic capacitance, and a floating diffusion region is formed to enhance light collection and signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistor structures are used, then manufacturing process is simple, but parasitic capacitance increases and noise increases
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to three-dimensional protruding structures with insulating sidewalls. This dimensional change allows the transistor channel to extend vertically, increasing the effective channel area without increasing the planar footprint, thereby reducing parasitic capacitance while maintaining manufacturing feasibility through adapted fabrication processes.
Solution Approach 2:
The transistor structure is segmented into distinct regions: the protruding channel region and the insulating sidewall regions. This segmentation isolates the channel from adjacent structures, reducing parasitic capacitance between the channel and surrounding elements while allowing independent optimization of each region's properties.
2Area of stationary object
If pixel size is reduced to save chip area, then chip area decreases, but light-sensitive area decreases and image quality deteriorates
Solution Approach 1:
By implementing three-dimensional protruding transistor structures with vertical channels, the patent increases the effective transistor area within the same planar pixel footprint. This allows for better transistor performance (lower noise, lower parasitic capacitance) without increasing the pixel size, thereby maintaining light-sensitive area while improving image quality.
Solution Approach 2:
The insulating sidewalls are nested around the protruding channel structures, creating a compact integrated design where the isolation structure is embedded within the transistor formation process itself. This nested arrangement maximizes space utilization within the pixel, allowing improved transistor performance without increasing overall pixel dimensions.
3Reliability
If more transistors are added to improve pixel functionality, then device performance improves, but chip area increases
Solution Approach 1:
The three-dimensional protruding structures with vertical channels provide increased effective transistor area and improved electrical performance within a compact planar footprint. This allows the same level of device performance to be achieved with fewer transistors or smaller transistor dimensions, thereby reducing the overall chip area requirement.
Data Source
AI summary
A method for forming a backside illuminated image sensor with a three-dimensional transistor structure is provided, where forming a gate of the three-dimensional transistor structure includes: forming a source follower transistor and/or a reset transistor with a three-dimensional transistor structure, wherein the source follower transistor and/or the reset transistor correspond to a protruding structure; and forming an insulating sidewall around the protruding structure, forming a groove between the insulating sidewall and a channel region of a transistor corresponding to the protruding structure, and forming a gate of the transistor in the groove, wherein the gate of the transistor is isolated by the insulating sidewall.