BSI Image Sensor Backside Pit Structure for Higher Quantum Efficiency
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Solution Overview
Problem
Conventional Back Side Illuminated (BSI) CMOS image sensors face limitations in light absorption efficiency and quantum efficiency due to reflection and non-uniform photo response.
Innovation Solution
The semiconductor device incorporates a semiconductor layer with a tilted lattice plane on its surface, featuring pyramid or prism pit portions that enhance light scattering and refraction, thereby improving absorption efficiency and quantum efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional BSI CMOS image sensors are used, then light sensitivity and quantum efficiency are improved, but reflection losses and non-uniform photo response occur
Solution Approach 1:
The patent applies curved surface structures (pyramid or prism shapes) on the backside of the semiconductor substrate to scatter and refract incident light. These non-planar geometric features redirect light paths, reducing direct reflection and increasing the probability of light absorption by photodiodes, thereby resolving the contradiction between light sensitivity and reflection losses.
Solution Approach 2:
The patent modifies the surface geometry parameters of the semiconductor substrate by creating tilted lattice planes with specific orientations (e.g., <110> or <100> crystal planes). This parameter change in surface topology transforms the optical interaction, converting specular reflection into diffuse scattering and improving light absorption efficiency while maintaining structural integrity.
2Reliability
If deep trench isolation structures are added to improve pixel isolation, then cross talk is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent combines the isolation function with the existing backside surface structure by forming pyramid or prism shapes that serve dual purposes: optical scattering and pixel isolation. The isolation structures are integrated into the same fabrication sequence as the surface texturing, merging multiple functions into a unified structure rather than adding separate isolation components.
Solution Approach 2:
The patent implements localized isolation structures positioned specifically at pixel boundaries on the backside surface. The isolation regions are created with specific geometric characteristics (e.g., deeper etching at pixel edges) that provide enhanced isolation precisely where needed, while maintaining optical scattering properties in the active photodiode regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances the quantum efficiency of the semiconductor device by reducing reflection and increasing light absorption, leading to improved image quality and performance.
Implementation Method 1
pyramid or prism pit portions that enhance light scattering and refraction
Implementation Method 2
pyramid or prism pit portions that enhance light scattering and refraction
Implementation Method 3
photodiode and other elements, to absorb light and convert the absorbed light into digital data or electrical signals
Data Source
AI summary
A device includes a plurality of photodiode regions within a semiconductor substrate, a plurality of transistors, a plurality of deep trench isolation (DTI) structures, and a plurality of isolation structures. The transistors are over a front-side surface of the semiconductor substrate. The DTI structures extend a first depth from a backside surface of the semiconductor substrate into the semiconductor substrate. The isolation structures extend a second depth from the backside surface of the semiconductor substrate into the semiconductor substrate. The second depth is less than the first depth. From a plan view, each of the plurality of isolation structures has a triangular profile at the backside surface of the semiconductor substrate.