BSI Image Sensor Silicide Thickness Control
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Solution Overview
Problem
The reduction in pixel size of image sensors makes it difficult to control the quality of pixels, leading to increased dark current and noise, particularly due to high resistance in the silicide region between contacts and the semiconductive substrate, resulting in black pixels that fail to produce proper image signals.
Innovation Solution
The implementation of a back side illuminated (BSI) image sensor with a silicide layer of predetermined thickness in the contact plug, formed through a process involving plasma ignition power and thermal anneals, to reduce resistance and improve pixel performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to increase resolution, then image sensor resolution is improved, but dark current and noise increase due to high resistance in silicide region
Solution Approach 1:
The patent changes the physical parameters of the silicide layer by controlling its thickness to be between 50-150 nm and adjusting its formation conditions (plasma ignition power, thermal anneal temperature and time) to achieve optimal electrical resistance that minimizes dark current while maintaining pixel functionality at reduced sizes
Solution Approach 2:
The silicide layer is formed preliminarily during the manufacturing process before final pixel assembly, using plasma ignition and thermal annealing steps to pre-establish the low-resistance contact between the contact plug and semiconductive substrate, preventing dark current issues before they manifest in the finished device
2Measurement precision
If pixel size is reduced, then image sensor resolution is improved, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent establishes specific parameter ranges for silicide layer thickness (50-150 nm) and formation conditions that provide a manufacturing window balancing resolution requirements with quality control, making it easier to produce consistent high-resolution sensors
Solution Approach 2:
The silicide layer formation process uses self-aligned plasma ignition and thermal annealing that automatically adjust to local conditions, reducing the need for manual precision adjustments and improving manufacturing consistency across different pixel batches
3Object-affected harmful factors
If silicide layer thickness is increased to reduce resistance, then dark current is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent optimizes the silicide layer thickness to a specific range (50-150 nm) that achieves adequate resistance reduction without requiring excessively thick layers, thereby limiting the increase in manufacturing complexity to a manageable level
Solution Approach 2:
The silicide layer formation is integrated into the continuous manufacturing flow with plasma ignition and thermal annealing steps that follow directly from previous processing stages, eliminating the need for separate complex manufacturing operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the resistance in the silicide region, enhancing the image sensor's ability to produce accurate image signals by minimizing dark current and noise, thereby improving the overall performance of the image sensor.
Implementation Method 1
high resistance in the silicide region between contacts and the semiconductive substrate, resulting in black pixels that fail to produce proper image signals
Implementation Method 2
formed through a process involving plasma ignition power and thermal anneals
Implementation Method 3
formed through a process involving plasma ignition power and thermal anneals
Data Source
AI summary
Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.