BSI Image Sensor Via Layout for Capacitor Space Constraints
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Solution Overview
Problem
Highly integrated image sensors face challenges in securing space for vias around capacitors due to the space occupied by the capacitors, making it difficult to efficiently arrange vias in existing image sensor designs.
Innovation Solution
The image sensor incorporates both edge vias and central vias efficiently arranged around the capacitors, with edge vias along the edges and central vias interposed between the capacitors, allowing for improved integration and space utilization without altering the shape of the electrode pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a backside illumination (BSI) structure is used to improve light-receiving efficiency, then sensitivity is improved, but wiring structure complexity increases
Solution Approach 1:
The wiring structure is segmented into distinct functional components: edge vias positioned at pixel boundaries and central vias positioned within pixel regions. This segmentation allows independent optimization of each via type, simplifying the overall wiring structure while maintaining BSI sensitivity advantages.
Solution Approach 2:
The patent introduces an intermediary wiring layer structure that mediates between the photoelectric conversion layer and upper capacitor structures. This intermediary layer organizes signal paths and reduces direct wiring complexity in the BSI configuration.
2Adaptability or versatility
If integration density is increased to improve device functionality, then global shutter operation is enabled, but manufacturing precision requirements increase
Solution Approach 1:
Different via structures are implemented in different local regions: edge vias with specific dimensions and positions at pixel boundaries, and central vias with different dimensions and positions within pixel regions. This local quality differentiation enables global shutter functionality while managing manufacturing precision requirements through region-specific design optimization.
3Reliability
If capacitor size is increased to improve charge storage for global shutter, then image quality improves, but pixel area increases reducing integration
Solution Approach 1:
The capacitor structure extends in the vertical dimension with multiple stacked layers (first capacitor layer, second capacitor layer) rather than only expanding horizontally. This dimensional transition allows increased charge storage capacity while maintaining compact pixel footprint, enabling global shutter operation without sacrificing integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement enables efficient placement of vias around capacitors, enhancing the integration and performance of the image sensor by optimizing the use of space, thereby improving the overall integration and functionality of the image sensor.
Implementation Method 1
a photoelectric conversion layer in the substrate
Data Source
AI summary
An image sensor includes a plurality of unit pixels, each including: a substrate including first and second sides which are opposite to each other, a photoelectric conversion layer in the substrate, and a wiring structure on the first side of the substrate. The wiring structure may include: a first capacitor, a second capacitor spaced from the first capacitor, a plurality of edge vias arranged along edges of the unit pixel, and a plurality of central vias interposed between the first capacitor and the second capacitor.