BSI Imager Metal Capacitor Placement Reduces Column Height
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Solution Overview
Problem
Conventional back-side illuminated (BSI) imagers have increased column height due to the positioning of column sample and hold (S/H) capacitors above and/or below the pixel array, which results in a larger imager size and higher column noise due to the use of smaller poly-silicon capacitors.
Innovation Solution
Positioning metal sample and hold parasitic capacitors on the front side of the BSI imager, overlapping the pixels, allows for the use of larger metal-to-metal parallel plate capacitors, reducing column height and noise while simplifying the design by eliminating the need for poly-silicon capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If column S/H capacitors are positioned above and/or below the pixel array, then the imager structure is conventional and easy to manufacture, but the column height increases and imager size becomes larger
Solution Approach 1:
The patent applies dimensionality change by moving the S/H capacitors from the vertical dimension (above/below pixel array) to the horizontal dimension (overlapping pixel array area on the same plane). This allows the capacitors to be positioned in the lateral space rather than extending the column height vertically, thereby reducing the imager's overall height while maintaining manufacturing feasibility through standard CMOS processes.
2Ease of manufacture
If poly-silicon capacitors are used in conventional BSI imagers, then the manufacturing process is established, but column noise increases
Solution Approach 1:
The patent applies parameter changes by transitioning from poly-silicon capacitor material to metal capacitor material. This material parameter change fundamentally alters the electrical characteristics, specifically reducing column noise while maintaining compatibility with established CMOS manufacturing processes. The metal capacitors provide lower noise performance due to their superior electrical properties compared to poly-silicon.
3Object-generated harmful factors
If metal-to-metal parallel plate capacitors are used, then column noise is reduced and capacitor size can be increased, but the imager structure becomes more complex
Solution Approach 1:
The patent applies merging by integrating the S/H capacitors with the pixel array structure itself, positioning them to overlap the pixel area rather than requiring separate dedicated space. This merging approach allows the use of larger metal-to-metal parallel plate capacitors with lower noise while avoiding additional structural complexity, as the capacitors share the same lateral footprint with the pixels they serve.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the overall column height of the imager and minimizes column noise by utilizing larger, simpler metal capacitors that do not increase the imager size, providing a tradeoff between capacitor size and noise levels.
Implementation Method 1
Positioning metal sample and hold parasitic capacitors on the front side of the BSI imager, overlapping the pixels, allows for the use of larger metal-to-metal parallel plate capacitors
Data Source
AI summary
The present invention relates to a backside illuminated (BSI) imager having a plurality of layers. A plurality of pixel sensors are positioned on a first layer of a substrate. Pixel select conductors are positioned on the substrate in front of the first layer. Pixel readout conductors including a plurality of output lines, pixel power conductors, and a ground conductor are positioned on the substrate in front of the pixel select conductors. A plurality of sample and hold capacitors coupled to the pixel output lines are positioned vertically and/or horizontally on the substrate in front of the ground conductor.