BSI Image Sensor Bond Pad Array for Reliable Face-to-Face Packaging
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Solution Overview
Problem
Current CMOS image sensor packaging methods face challenges in reducing package area and reliability due to the dishing effect caused by large bond pads, which affects bonding reliability and current conduction.
Innovation Solution
The use of a bond pad array with smaller, interconnected bond pads at the same or different metal layers, allowing face-to-face bonding of CMOS sensors and ASICs without a conventional carrier wafer, thereby reducing the dishing effect and enhancing bonding reliability and current conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large bond pads are used for bonding CMOS sensors and ASICs, then bonding area is sufficient, but dishing effect occurs reducing bonding reliability
Solution Approach 1:
The patent divides a single large bond pad into multiple smaller bond pads arranged in an array configuration. This segmentation eliminates the dishing effect that occurs with large bond pads while maintaining sufficient total bonding area. The smaller individual pads do not suffer from dishing, and their collective area provides adequate bonding surface for reliable connection between CMOS sensors and ASICs.
Solution Approach 2:
The patent transitions from a single-plane large bond pad to a multi-layer bond pad array structure. Bond pads are distributed across multiple metal layers (e.g., M1, M2, M3) vertically stacked, creating a three-dimensional bonding architecture. This dimensional change allows current to flow through multiple parallel paths and eliminates the dishing effect inherent in large two-dimensional pads.
2Area of stationary object
If conventional carrier wafer is used for bonding, then bonding process is simplified, but package area increases
Solution Approach 1:
The patent extracts and eliminates the conventional carrier wafer from the bonding process. By using face-to-face bonding with complementary bond pad arrays directly on the CMOS sensor and ASIC, the intermediate carrier wafer is removed. This extraction significantly reduces the overall package area while the direct bonding method maintains manufacturing feasibility through precise alignment of the bond pad arrays.
Solution Approach 2:
The bond pad arrays are designed with self-aligning features where pads on one device directly correspond to pads on the mating device. The complementary arrangement of bond pads enables automatic alignment during bonding without requiring a carrier wafer for positioning, allowing the devices to bond to each other directly in a self-service manner.
Data Source
AI summary
Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.