Stacked BSI Image Sensor Architecture for Photodiode-Logic Separation
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Solution Overview
Problem
Existing backside illuminated (BSI) CMOS image sensors face compromised electrical performance due to the need for photo diodes to be formed over a large area, which limits the space for transistors and logic circuits, affecting overall performance and efficiency.
Innovation Solution
A vertically integrated BSI image sensor design, where photo-sensitive elements, pixel transistors, and logic circuits are formed on separate chips, allowing for independent manufacturing and operation, with advanced technology nodes used for logic circuits to improve performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If photo diodes are formed over a large area in BSI CMOS image sensors, then photonic performance is improved, but electrical performance deteriorates due to limited space for transistors and logic circuits
Solution Approach 1:
The patent divides the image sensor into multiple separate chips: a first chip containing photo diodes and a second chip containing transistors and logic circuits. This segmentation allows each chip to be optimized independently - the first chip can have large-area photo diodes for improved photonic performance, while the second chip can have densely packed transistors and logic circuits for improved electrical performance, thereby resolving the contradiction between photonic and electrical performance
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture where the first chip with photo diodes is bonded to the second chip with transistors. This vertical stacking in the third dimension allows both large-area photo diodes and complex transistor circuits to coexist without competing for the same two-dimensional space, enabling simultaneous optimization of both photonic and electrical performance
2Measurement precision
If photo diodes occupy large area on the same chip, then light sensitivity is improved, but device complexity increases due to integration constraints
Solution Approach 1:
By separating the photo diode array onto a dedicated first chip and the transistor circuitry onto a second chip, the patent eliminates the integration constraints that would otherwise force compromises in either photo diode area or circuit complexity. Each chip can be independently designed and manufactured with optimal layout, reducing overall device complexity while maintaining high light sensitivity
Solution Approach 2:
The patent changes the architectural parameter from monolithic integration to heterogeneous stacking, fundamentally altering how the system manages the trade-off between light sensitivity and device complexity. This parameter change enables independent optimization of photo detection area and circuit complexity, allowing high light sensitivity without proportionally increasing integration constraints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances photonic and electrical performance by optimizing chip area usage, improving power efficiency, and allowing for more advanced transistor integration, thereby increasing the image sensor's overall performance and efficiency.
Implementation Method 1
a first chip comprising a plurality of photo-sensitive devices
Data Source
AI summary
A semiconductor device includes a first chip comprising a plurality of photo-sensitive devices, wherein the plurality of photo-sensitive devices are formed as a first array. The semiconductor device includes a second chip bonded to the first chip and comprising: a plurality of groups of pixel transistors, wherein the plurality of groups of pixel transistors are formed as a second array; and a plurality of input/output transistors, wherein the plurality of input/output transistors are disposed outside the second array. The semiconductor device includes a third chip bonded to the second chip and comprising a plurality of logic transistors.