Back-Side Illuminated Image Sensor Pad Layout for Planar BCFA Integration
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Solution Overview
Problem
The integration of a buried color filter array (BCFA) with CMOS image sensor processes is challenging due to the requirement of a substantially planar light-receiving surface, which is often disrupted by scribe line openings, leading to passivation layer damage and compromised optical performance.
Innovation Solution
A method is introduced where a flat pad structure is formed within the scribe line opening, allowing for a subsequent planarization process that ensures the passivation layer is formed after pad and dielectric layer formation, thereby avoiding damage and enhancing optical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scribe line openings are formed in the semiconductor substrate, then the substrate can be divided into individual sensor chips, but the light-receiving surface becomes non-planar causing passivation layer damage and reduced optical performance
Solution Approach 1:
The patent performs pad formation and dielectric layer deposition before forming the scribe line openings. This preliminary action ensures that the passivation layer is already in place and protected when the substrate is divided, preventing passivation layer damage during the substrate division process while maintaining surface planarity for optimal optical performance
2Ease of manufacture
If the passivation layer is formed early in the process, then subsequent processing is simplified, but the passivation layer becomes vulnerable to damage during scribe line opening formation
Solution Approach 1:
The pad structure and dielectric layer are formed preliminarily before scribe line opening formation, creating a protective framework that simplifies subsequent processing while ensuring passivation layer integrity during substrate division
3Productivity
If the light-receiving surface is made non-planar to accommodate scribe line openings, then substrate division is enabled, but optical performance deteriorates
Solution Approach 1:
The patent resolves the surface planarity issue by transitioning to another dimension - forming the pad structure with specific vertical layering (conductive pad, dielectric layer, planarization layer) that maintains a planar upper surface while accommodating the scribe line openings below, thus preserving optical performance while enabling substrate division
Data Source
AI summary
A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.