Backside Illuminated Image Sensor Stacked Die Packaging
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Solution Overview
Problem
Current image sensor packaging in 3D integrated circuits requires larger carrier wafers due to the need for extensive connections between MOS sensors and their associated ASICs, leading to increased package area and costs.
Innovation Solution
The control circuitry is moved to a separate ASIC die mounted on the non-illuminated side of the sensor die, allowing for a stacked die structure where the sensor die and control circuit die are bonded, reducing the number of connections needed and enabling a more compact package by using a redistribution layer and bonding pads to route connections between pixels and bond pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOS sensor and ASIC are bonded to carrier wafer in parallel, then connections between sensor and ASIC are established, but package area increases
Solution Approach 1:
The patent transitions from a planar parallel bonding architecture to a three-dimensional stacked architecture. The sensor die and ASIC die are bonded vertically in stacks, utilizing the vertical dimension to reduce the horizontal footprint on the carrier wafer. This dimensional change allows multiple sensor-ASIC pairs to share the same carrier wafer area, directly reducing the package area while maintaining all necessary electrical connections.
Solution Approach 2:
The patent implements a hierarchical nesting structure where sensor dies and ASIC dies are nested vertically in stacks on the carrier wafer. Each stack contains a sensor die with its corresponding ASIC die bonded to it, creating a nested arrangement that maximizes space utilization. This nesting approach allows the system to accommodate multiple independent sensor-ASIC connections within a reduced overall package area.
2Adaptability or versatility
If extensive connections are made between MOS sensor and ASIC, then functional requirements are met, but device complexity increases
Solution Approach 1:
The patent merges the sensor die and ASIC die into integrated vertical stacks, combining multiple functional components into unified structures. By bonding the ASIC directly to the sensor die in a stacked configuration, the patent reduces the number of separate connection points and interconnect requirements compared to parallel bonding, thereby simplifying the overall device complexity while maintaining full functional capability.
3Reliability
If larger carrier wafer is used, then more connections can be accommodated, but manufacturing costs increase
Solution Approach 1:
The patent utilizes vertical stacking to increase connection capacity without proportionally increasing carrier wafer area. By arranging sensor-ASIC pairs in vertical stacks, the system can accommodate multiple connections within a smaller horizontal footprint, reducing carrier wafer size requirements and associated manufacturing costs while maintaining or enhancing connection capacity.
Data Source
AI summary
A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.