Backside Illumination Image Sensor Wafer Bonding via Vias
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Solution Overview
Problem
Conventional image sensors manufactured through 3D CMOS image sensor processes face issues with deteriorating pixel characteristics due to parasitic capacitance and insufficient process margins caused by misalignment during the bonding of wafers.
Innovation Solution
The solution involves electrically connecting two wafers using the vias of one wafer and the bonding pads of the other, simplifying the manufacturing process, reducing parasitic capacitance, and enhancing the misalignment margin by omitting bonding pads on one wafer and using vias for electrical connection, thereby improving pixel characteristics and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding pads are formed on both wafers to establish electrical connection, then electrical connection between wafers is achieved, but parasitic capacitance increases and pixel characteristics deteriorate
Solution Approach 1:
The patent removes bonding pads from one of the two wafers, keeping them only on the first wafer. This extraction eliminates the parasitic capacitance that would be generated by bonding pads on both wafers, while still achieving the necessary electrical connection through the remaining bonding pads and vias.
Solution Approach 2:
The patent merges the electrical connection function into the via structure. By making the via on the second wafer extend through the entire thickness to expose the metal layer directly at the bonding surface, the via serves both as a structural support and as the electrical connection interface, eliminating the need for separate bonding pads on the second wafer.
2Reliability
If bonding pads are formed on both wafers, then electrical connection is established, but process margin becomes insufficient due to misalignment
Solution Approach 1:
By removing bonding pads from the second wafer, the patent reduces the number of critical alignment features that must match between wafers. This extraction of unnecessary bonding pads from one wafer increases the misalignment margin and reduces the precision requirements for the bonding process.
3Reliability
If bonding pads are formed on both wafers, then electrical connection is achieved, but manufacturing process becomes complex
Solution Approach 1:
The patent extracts the bonding pad formation process from the second wafer manufacturing sequence. This eliminates the need to form, pattern, and etch bonding pads on the second wafer, thereby simplifying the manufacturing process and reducing process steps.
Solution Approach 2:
The patent merges the via formation and electrical connection functions. The via on the second wafer is formed to extend through the entire thickness of the wafer, combining the structural support function of the via with the electrical connection function that would otherwise require separate bonding pads.
4Object-generated harmful factors
If vias are used for electrical connection without bonding pads on one wafer, then parasitic capacitance is reduced, but bonding force may be compromised
Solution Approach 1:
The patent merges the via structure to serve dual purposes: providing mechanical support for bonding and establishing electrical connection. The via on the second wafer extends through the entire thickness to expose the metal layer at the bonding surface, creating a robust bonding interface that maintains bonding force while eliminating parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces parasitic capacitance, improves pixel characteristics, and increases the manufacturing yield by securing a larger misalignment margin, while maintaining a strong bonding force even when top and bottom metal pitches differ.
Implementation Method 1
a plurality of backside illumination photodiodes which sense light incident from a backside and output signals
Data Source
AI summary
A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.