BSPDN Die Integration Using Dual Substrates for Thickness Matching
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Solution Overview
Problem
The challenge in heterogeneous integration processes is compensating for significant thickness differences between advanced device dies with backside power distribution networks (BSPDN) and regular logic dies, which are typically not compatible with existing adhesive padding methods.
Innovation Solution
A semiconductor structure is developed with a backside power distribution network (BSPDN) and a frontside substrate, along with a backside substrate, to adjust the overall thickness of device dies to match that of logic and memory dies, using C4 bumps and through-silicon-vias for integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If adhesive padding is used to compensate thickness difference, then thickness mismatch can be compensated, but it becomes ineffective when thickness difference is too large (e.g., 15 μm or more)
Solution Approach 1:
The substrate is divided into two separate substrates: a first substrate attached to the BEOL structure and a second substrate attached to the BSPDN structure. This segmentation allows independent thickness control of each substrate, enabling the overall device die thickness to be adjusted to match surrounding logic and memory dies even when the thickness difference is as large as 15 μm or more.
Solution Approach 2:
The first and second substrates act as intermediary elements that bridge the thickness gap between the thin device die (with BSPDN) and the thicker surrounding logic/memory dies. These substrates are bonded to the device die and can be designed with appropriate thicknesses to compensate for the overall thickness mismatch, making heterogeneous integration feasible.
2Use of energy by moving object
If substrate is thinned to device level for BSPDN, then power distribution efficiency is improved, but thickness difference from regular logic die becomes too large to compensate
Solution Approach 1:
By segmenting the substrate into first and second substrates, the invention maintains the thin device die thickness (3-5 μm) for optimal power distribution efficiency while using the separate first and second substrates to compensate for the overall thickness mismatch during heterogeneous integration.
Solution Approach 2:
The first substrate is designed with a thickness that compensates for the overall thickness difference between the thin device die and surrounding logic/memory dies. This local quality adjustment at the substrate level allows the device die to maintain its thin profile for efficient power distribution while still achieving thickness matching in the integrated package.
3Productivity
If device die thickness is reduced for BSPDN, then integration density is improved, but compatibility with existing logic die becomes problematic
Solution Approach 1:
The substrate is segmented into first and second substrates that can be independently designed with appropriate thicknesses. This allows the device die to be thin (3-5 μm) for high integration density while the combined structure (device die + first substrate + second substrate) achieves thickness compatibility with surrounding logic dies for seamless heterogeneous integration.
Solution Approach 2:
The first and second substrates serve as intermediary elements that enable compatibility between thin device dies with BSPDN and thicker logic dies. These substrates are bonded to both the device die and surrounding dies, facilitating heterogeneous integration of different thickness components in a unified package structure.
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The structure includes a device die including a device layer; a back-end-of-line (BEOL) structure on a frontside of the device layer and a frontside substrate attached to the BEOL structure; and a backside power distribution network (BSPDN) structure on a backside of the device layer and a backside substrate attached to the BSPDN structure; and a device package including a base element and a lid element, wherein the device die is attached to the base element of the device package through multiple C4 bumps at the frontside substrate and is attached to the lid element of the device package at the backside substrate. A method of forming the same is also provided.