BSPDN Layout for Small- and Large-CPP Power Routing
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in managing power distribution networks, particularly in small-CPP areas where routing complexity and excessive IR drops occur, and in large-CPP areas where space constraints limit efficient formation of semiconductor elements.
Innovation Solution
The implementation of a backside power distribution network (BSPDN) structure at both small-CPP and large-CPP areas, which includes specific source/drain structures, contact structures, via structures, and metal lines to facilitate effective power distribution and area gain, while maintaining device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If BSPDN structure is formed in small-CPP area, then routing complexity is reduced and IR drop is prevented, but manufacturing complexity increases due to additional backside contact and metal line structures
Solution Approach 1:
The patent moves the power distribution network from the front side to the back side of the semiconductor device, utilizing the third dimension (depth/substrate side) to resolve routing complexity. By forming backside contact structures and metal lines on the opposite side of the substrate from the transistor gates, the design provides additional routing space and reduces congestion in small-CPP areas without affecting front-side device layout.
Solution Approach 2:
The power distribution network is segmented into frontside and backside components. The backside contact structures connect to source/drain regions through the substrate, while frontside metal lines handle local routing. This segmentation allows independent optimization of each layer, reducing overall system complexity despite adding backside structures.
2Area of stationary object
If BSPDN structure is formed in small-CPP area, then area gain is achieved, but manufacturing process complexity increases due to additional BEOL process steps
Solution Approach 1:
The backside contact structures and backside metal lines are merged into a unified BSPDN structure that serves multiple functions: providing power distribution, reducing IR drop, and enabling area-efficient layout. By combining these elements on the backside, the patent achieves area gain without proportionally increasing process complexity, as the structures share common fabrication steps.
Solution Approach 2:
Utilizing the backside of the substrate provides an additional dimensional space for power distribution, effectively doubling the available routing area. This dimensional expansion enables area gain by allowing parallel power and signal routing without increasing the device footprint, while process complexity is managed through integrated fabrication sequences.
3Ease of manufacture
If conventional FSPDN is used in large-CPP area, then manufacturing process is simpler, but routing efficiency and power distribution performance are limited
Solution Approach 1:
The BSPDN structure is designed to be universally applicable across both small-CPP and large-CPP areas, replacing the need for area-specific power distribution approaches. The backside contact structures and metal lines provide consistent power distribution benefits regardless of front-side gate pitch, enabling simplified manufacturing through standardized processes while improving power distribution efficiency uniformly across the device.
Solution Approach 2:
By migrating power distribution to the backside substrate surface, the patent unlocks additional routing space that is available in both small-CPP and large-CPP areas. This dimensional transition improves power distribution efficiency by providing longer, less congested metal line paths and better access to power rails, while maintaining manufacturing simplicity through adapted standard fabrication processes.
4Reliability
If backside contact structure connects to bottom surface of source/drain structure, then IR drop is prevented, but structural complexity increases
Solution Approach 1:
The power distribution function is extracted from the front-side metal line network and relocated to the backside substrate. By taking out the power distribution network from the congested front-side layout and placing it on the backside, the patent reduces IR drop through improved current path geometry while managing structural complexity through separate layer processing.
Solution Approach 2:
The substrate acts as an intermediary medium connecting the backside contact structures to the source/drain regions. Current flows from backside contacts through the substrate to reach the device active regions, providing a low-resistance path that prevents IR drop. This intermediary approach manages structural complexity by utilizing the existing substrate as the current conduction medium rather than requiring additional complex interconnect structures.
Data Source
AI summary
Provided is a semiconductor device in which a large-CPP area includes a 1st source/drain structure; a 1st frontside contact structure, at a front side of the semiconductor device, connected to the 1st source/drain structure; a 1st via structure, at a lateral side of the 1st source/drain structure, connected to the 1st frontside contact structure; a 2nd via structure on the 1st frontside via structure; a 1st frontside metal line, at the front side of the semiconductor device, connected to the 2nd via structure; and a 1st backside metal line, at a back side of the semiconductor device, connected to the 1st via structure.