BSPDN Semiconductor Layout With Lateral PN Junction Integration
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Solution Overview
Problem
The back side thinning process for semiconductor devices often results in insufficient space for forming passive devices or PN junction devices due to the removal of substrates for back side power delivery networks, leading to routing congestion and reduced device density.
Innovation Solution
Incorporating a back side power delivery network (BSPDN) structure with integrated passive devices or PN junction devices in a semiconductor device, where transistors are formed in one layer and the BSPDN structure is in another layer below, connected to the transistors to facilitate power delivery and alleviate routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the substrate is removed to provide BSPDN structure, then power delivery capability is improved, but space for passive devices and PN junction devices is reduced
Solution Approach 1:
The patent moves passive devices and PN junction devices from the traditional planar layout to a vertical stacking configuration. Specifically, these devices are formed in a second layer below the first layer containing transistors, utilizing the vertical dimension to accommodate additional functional elements without increasing the lateral footprint. This dimensional transition resolves the contradiction by providing space for power delivery structures while preserving area for passive components through three-dimensional integration.
Solution Approach 2:
The patent segments the semiconductor device into distinct vertical layers: a first layer containing transistors and a second layer containing passive devices and PN junction devices. This segmentation allows independent optimization of each layer's function - the first layer handles active switching while the second layer provides power delivery and passive functionality. By dividing the device structure into functional segments across layers, the patent simultaneously achieves adequate power delivery capability and sufficient space for passive components.
2Device complexity
If substrate is thinned for BSPDN, then routing complexity is reduced, but device density is reduced
Solution Approach 1:
The patent addresses the device density issue by transitioning from two-dimensional planar integration to three-dimensional vertical integration. Passive devices and PN junction devices are positioned in a second layer beneath the transistor layer, effectively utilizing the vertical dimension to pack more functionality into the same lateral footprint. This dimensional change maintains high device density while simplifying routing by separating power delivery paths in the lower layer from signal paths in the upper layer.
Solution Approach 2:
The patent segments routing functions by assigning different layers to different routing purposes. The first layer handles transistor interconnects and signal routing, while the second layer handles power delivery routing through BSPDN structures and passive device connections. This functional segmentation of routing across layers reduces overall routing complexity without sacrificing device density, as each layer can be optimized independently for its specific routing requirements.
Data Source
AI summary
Provided is a semiconductor device that includes: at least one field-effect transistor and at least one PN junction device at a lateral side of the at least one field-effect transistor in a 1st layer; and at least one back side power delivery network (BSPDN) structure in a 2nd layer below the 1st layer, wherein the at least one BSPDN structure is configured to connect the at least one field-effect transistor to a voltage source.