Blind Source Separation Filter Pipelining for Low-Latency Signal Tracking
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Solution Overview
Problem
Existing signal processing systems face challenges in efficiently separating and identifying signals of interest from mixed signals due to high hardware latencies, memory, and computational resource requirements, particularly in pipelining and parallelizing blind source separation filters, which can lead to misclassification of signals and the need for different hardware versions for various platforms.
Innovation Solution
The implementation of a signal data processor with pipelined and parallelized blind source separation modules that generate pulse descriptor words, allowing for real-time identification and tracking of signal parameters using significantly reduced lookup tables and minimal computational resources, enabling continuous filter tuning and accurate signal parameter tracking with low hardware latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pipelining and parallelizing techniques are used in blind source separation filters, then signal separation performance is improved, but memory and computational resource requirements increase significantly
Solution Approach 1:
The filter is divided into multiple independent parallel filters, each processing a specific frequency band. This segmentation allows the system to achieve high-performance signal separation through parallel processing while managing computational resources by distributing work across multiple smaller, specialized filter units rather than one large complex filter
Solution Approach 2:
Filter coefficients are pre-calculated and stored in lookup tables before runtime. During operation, the system performs preliminary selection of appropriate coefficients based on desired frequency characteristics, avoiding the need for complex real-time coefficient calculations and reducing computational resource requirements during actual signal processing
2Measurement precision
If new filter coefficients are determined for each tuned frequency using pipelining techniques, then filter accuracy is improved, but hardware latency increases causing signal misclassification
Solution Approach 1:
Filter coefficients for multiple frequency points are pre-calculated and stored in lookup tables before the filter operates. When a specific frequency is needed, the system quickly retrieves the pre-computed coefficients through interpolation rather than calculating them in real-time, maintaining high filter accuracy while minimizing hardware latency and preventing signal misclassification
Solution Approach 2:
The system dynamically selects and interpolates between pre-stored filter coefficients based on the desired tuned frequency. This dynamic coefficient selection allows the filter to adapt to different frequency requirements with high accuracy while avoiding the time-consuming process of real-time coefficient generation for each frequency change
3Adaptability or versatility
If large lookup tables are used to store filter coefficients for each frequency, then filter tuning flexibility is improved, but memory requirements increase excessively
Solution Approach 1:
Instead of storing complete filter coefficient sets for every possible frequency point, the system stores coefficients for a limited set of representative frequency points in the lookup table. The full tuning flexibility is achieved through interpolation between these partial coefficient sets, reducing memory requirements while maintaining adaptability across the entire frequency range
Solution Approach 2:
The system changes the representation of filter coefficients by storing them in a compressed format based on key frequency points rather than continuous frequency data. Through parameter interpolation techniques, the system generates intermediate coefficient values as needed, achieving comprehensive filter tuning flexibility with significantly reduced memory storage requirements
4Ease of manufacture
If different circuit and hardware versions are created for various platforms, then platform-specific optimization is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The blind source separation filter is designed with a universal architecture that can operate on multiple hardware platforms (FPGA, ASIC, DSP) without requiring different circuit versions. The parallel filter structure with pre-computed coefficients provides platform-independent functionality, allowing the same design to be deployed across various hardware implementations while maintaining optimized performance on each platform
Data Source
AI summary
A method of processing a plurality of time-varying signals received at a sensor communicatively coupled to a signal data processor to identify at least one parameter of at least one of the plurality of time-varying signals is provided. The method includes receiving, at a plurality of blind source separation (BSS) modules of the signal data processor, signals derived from the plurality of time-varying signals, each BSS module of the plurality of BSS modules including a filtering subsystem having a pipelined architecture and a parallelized architecture. The method also includes generating a plurality of blind source separated signals, and transmitting at least one pulse descriptor word (PDW) parameter vector signal to a computing device of the signal data processor. The method further includes identifying the at least one parameter from the at least one PDW parameter vector signal, and outputting the at least one parameter from the signal data processor.