Blind Source Separation Filter Pipelining for Low-Latency Radar Signals
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Solution Overview
Problem
Existing signal processing systems face challenges in accurately separating and identifying signals of interest from mixed radar signals due to excessive hardware latencies, high memory and computational resource requirements, and the need for different circuit and hardware versions for various platforms, which can lead to misclassification of signals.
Innovation Solution
A signal processing system that employs a tunable blind source separation filter with a pipelined and parallelized architecture, enabling real-time processing and continuous filter tuning with low hardware latency, using a significantly smaller lookup table and reducing memory and computational resources, while supporting both FPGA- and ASIC-based designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pipelining and parallelizing techniques are used to improve filter performance, then signal separation accuracy is improved, but hardware latency increases and memory requirements increase
Solution Approach 1:
The filter is divided into multiple parallel filter banks, each processing different frequency components simultaneously. This segmentation allows the system to achieve high signal separation accuracy through parallel processing while maintaining low hardware latency by avoiding sequential operations.
Solution Approach 2:
The patent transforms the traditional single-filter sequential processing into a multi-dimensional parallel filter bank structure. By adding the frequency dimension with multiple parallel filters operating simultaneously, the system achieves both high accuracy and low latency through dimensional expansion of the processing architecture.
2Measurement precision
If pipelining and parallelizing techniques are used to improve filter performance, then signal separation accuracy is improved, but memory and computational resource requirements increase
Solution Approach 1:
The filter bank uses identical filter structures that can be reused across different frequency channels. This universal design allows the same hardware circuit to perform multiple functions by processing different frequency components in parallel, reducing overall memory and computational resource requirements while maintaining high signal separation accuracy.
Solution Approach 2:
The patent implements multiple copies of the same filter structure in parallel, where each copy handles a specific frequency band. This copying approach enables high accuracy through parallel processing while optimizing resource usage by using replicated simple structures rather than complex unique structures for each filter.
3Adaptability or versatility
If different circuit and hardware versions are used for various platforms, then platform-specific optimization is achieved, but device complexity and development difficulty increase
Solution Approach 1:
The filter bank architecture is designed as a universal platform that can be deployed across different hardware systems (FPGA, ASIC, DSP). The same parallel filter bank structure adapts to various platforms without requiring fundamentally different circuit designs, reducing device complexity while maintaining platform-specific optimization capabilities through parameter adjustment rather than structural change.
Data Source
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AI summary
A method 1200 of processing a plurality of time-varying signals 114/116 received at a sensor 103 communicatively coupled to a signal data processor 101 to identify at least one parameter of at least one of the plurality of time-varying signals 114/116 is provided. The method 1200 includes receiving 1202, at a plurality of blind source separation (BSS) modules 120 of the signal data processor 101, signals derived from the plurality of time-varying signals 114/116, each BSS module 120 of the plurality of BSS modules 120 including a filtering subsystem 207 having a pipelined architecture and a parallelized architecture. The method 1200 also includes generating a plurality of blind source separated signals 129, and transmitting at least one pulse descriptor word (PDW) parameter vector signal 138 to a computing device 132 of the signal data processor 101. The method 1200 further includes identifying the at least one parameter from the at least one PDW parameter vector signal 138, and outputting the at least one parameter from the signal data processor 101.