Coupled BT Base and FET Gate Structure for Compact CMOS Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Efficient integration of lateral bipolar transistors into the same device layer as field effect transistors in complementary metal oxide semiconductor (CMOS) process flows for semiconductor-on-insulator structures is a technical challenge.
Innovation Solution
A structure is designed with a bipolar transistor over a first back-gate well and a field effect transistor over an adjacent second back-gate well, where the gate structure of the FET is coupled to the base structure of the BT, allowing for a shared node without intervening elements, and independent or simultaneous biasing through back-gate terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lateral bipolar transistors are integrated into the same device layer as field effect transistors in CMOS process flows, then device integration efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the bipolar transistor base structure with the FET gate structure by forming them as a single integrated structure during the same fabrication process. The base of the bipolar transistor and the gate of the FET share common regions and are formed simultaneously, eliminating the need for separate processing steps and reducing manufacturing complexity while achieving high integration efficiency
Solution Approach 2:
The patent creates a multi-functional structure where certain regions serve dual purposes: the base region of the bipolar transistor also functions as part of the FET gate structure, and vice versa. This universal design allows a single structure to perform multiple functions (bipolar transistor operation and FET operation) without requiring additional separate components, thereby improving integration efficiency without proportionally increasing manufacturing complexity
2Area of moving object
If bipolar transistor base structure is coupled to field effect transistor gate structure, then surface area requirements are reduced, but device design complexity increases
Solution Approach 1:
The patent implements a nested structure where the bipolar transistor base is embedded within or adjacent to the FET gate structure, and vice versa. The base structure extends laterally between emitter/collector terminals and couples to the gate structure, creating a compact nested arrangement that maximizes space utilization. This nesting reduces the overall surface area required while the modular nested design actually simplifies fabrication compared to fully separate structures
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional integrated structure by having the base structure extend longitudinally away from the emitter/collector terminals and couple to the gate structure in multiple dimensions. This dimensional transition allows compact coupling that reduces surface area footprint while the systematic approach to 3D integration provides clear fabrication guidance that manages design complexity
3Use of energy by moving object
If gate structure is coupled to base structure with shared node, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the gate and base structures into a single integrated formation process where both structures are created simultaneously from the same material layers and processing steps. The shared node is an inherent feature of this merged structure rather than a separately formed connection, which reduces power consumption through direct coupling while actually lowering manufacturing precision requirements compared to forming separate structures and then connecting them with additional high-precision steps
Data Source
AI summary
Embodiments of the disclosure provide a structure including a first back-gate well adjacent a second back-gate well. A bipolar transistor (BT) is over the first back-gate well and includes a base structure laterally between a set of emitter/collector (E/C) terminals and extending longitudinally away from the set of E/C terminals. A field effect transistor (FET) is over the second back-gate well and includes a gate structure laterally between a set of source/drain (S/D) terminals and extending longitudinally away from the set of S/D terminals toward the BT. The gate structure is coupled to the base structure.