Branch Prediction Circuitry BTB Return Address Encoding
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Solution Overview
Problem
Existing branch prediction circuitry wastes storage resources by redundantly encoding return branch instructions and their target addresses in the branch target buffer (BTB), which can lead to inefficiencies in terms of circuit area and power consumption.
Innovation Solution
The proposed solution involves encoding BTB entries in such a way that they cannot simultaneously indicate the presence of a return branch instruction and its target address, with return branch predictions derived from a separate return address prediction structure, thereby optimizing storage and power usage without sacrificing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the BTB structure encodes both return branch indication and predicted target address for return branches, then complete branch information is available, but storage resources are wasted and circuit area increases
Solution Approach 1:
The patent extracts the return branch target address information from the BTB structure and stores it separately in a return address prediction structure. The BTB only stores an indication of whether a block contains a return branch, while the actual target addresses are maintained externally. This separation eliminates redundant storage of return branch target addresses in the BTB, reducing circuit area while preserving prediction accuracy through the dedicated return address prediction structure.
2Reliability
If the BTB structure encodes both return branch indication and predicted target address for return branches, then complete branch information is available, but power consumption increases
Solution Approach 1:
By extracting and removing the redundant return branch target address fields from the BTB structure, the patent reduces the number of bits that need to be written, read, and maintained in the BTB. This extraction reduces dynamic power consumption associated with BTB operations while maintaining complete branch prediction capability through the separate return address prediction structure.
Solution Approach 2:
The patent uses a separate return address prediction structure that maintains copies of return branch target addresses externally. Instead of storing redundant copies within the BTB, the system uses a dedicated structure that can be optimized independently, reducing the power burden on the BTB while ensuring accurate return address prediction is available when needed.
3Productivity
If the BTB structure uses encoding capable of indicating both return branch presence and target address, then no additional lookup is needed, but storage efficiency decreases
Solution Approach 1:
The patent extracts the return branch target address storage function from the BTB, leaving only a compact indication of return branch presence in the BTB entries. This extraction dramatically improves storage efficiency by eliminating redundant address fields. The return address prediction structure maintains the full target addresses separately, ensuring that when a return branch is detected, the target address can be retrieved without compromising prediction speed.
Data Source
AI summary
Branch prediction circuitry comprises: a return address prediction structure to store at least one predicted return address; and a branch target buffer (BTB) structure comprising entries each for specifying predicted branch information for a corresponding block of instructions. Within at least a subset of entries of the BTB structure, each entry specifies the predicted branch information with an encoding incapable of simultaneously indicating both: that the corresponding block of instructions is predicted to include a return branch instruction (for which the return address prediction structure is used to predict the target address); and the predicted target address for the return branch instruction. This can provide a more efficient BTB structure which requires less circuit area and power for a given level of branch prediction performance.