Branch Target Buffer Shortcut Path for Prediction Latency
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Solution Overview
Problem
Current data processing apparatuses face performance and power consumption issues due to the limitations of branch target buffers (BTBs) in predicting multiple branch instructions within a fetch block, leading to increased misprediction chances and latency.
Innovation Solution
The implementation of a branch target buffer with a shortcut path that bypasses the branch target selecting circuitry when a predetermined condition is satisfied, allowing for earlier identification of the next fetch block address and reducing prediction latency, especially in cases with only one hit in the BTB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the branch target buffer performs a full lookup and selection process for multiple predicted target addresses, then the accuracy of branch prediction is improved, but the prediction latency increases
Solution Approach 1:
The patent segments the branch target buffer lookup process into two independent paths: a shortcut path that directly forwards a single predicted target address, and a full path that performs comprehensive lookup and selection among multiple target addresses. This segmentation allows the system to choose the appropriate path based on the number of predicted branches, thereby reducing latency when only one target is needed while maintaining accuracy when multiple targets exist.
Solution Approach 2:
The shortcut path performs preliminary action by directly forwarding a predicted target address from the branch target buffer without waiting for the complete selection process. This preliminary forwarding occurs in parallel with the full lookup process, allowing the system to obtain prediction results faster when the predetermined condition (single predicted branch) is satisfied, thus reducing prediction latency.
2Adaptability or versatility
If the branch target buffer stores multiple predicted target addresses for multiple branch instructions in a fetch block, then the coverage of branch prediction is improved, but the device complexity increases
Solution Approach 1:
The patent extracts the complex selection logic from the main branch target buffer lookup path by implementing a separate shortcut path. This extraction removes the need for complex comparison and selection circuitry in the critical path, as the shortcut path directly forwards the predicted target address when the predetermined condition is met, thereby reducing device complexity while maintaining the capability to handle multiple branch instructions.
Solution Approach 2:
The patent introduces dynamic path selection based on a predetermined condition (whether the fetch block contains a single predicted branch or multiple predicted branches). The system dynamically chooses between the shortcut path (for single branch cases) and the full lookup path (for multiple branch cases), optimizing the balance between prediction coverage and device complexity adaptively rather than using a fixed complex structure for all cases.
3Speed
If the shortcut path is used to bypass the branch target selecting circuitry, then the prediction speed is improved, but the reliability of handling multiple branches may be reduced
Solution Approach 1:
The system dynamically adjusts the prediction path based on the predetermined condition regarding the number of predicted branches in the fetch block. When the condition indicates a single predicted branch, the shortcut path is activated for high-speed prediction. When the condition indicates multiple predicted branches, the system switches to the full lookup path, ensuring reliable handling of complex multi-branch scenarios. This dynamic adaptation resolves the contradiction by making reliability conditional on the branch scenario.
Solution Approach 2:
The predetermined condition check acts as an intermediary that determines whether to use the shortcut path or the full lookup path. This intermediary mechanism ensures that the shortcut path (which may have reduced reliability for multi-branch cases) is only used when appropriate (single branch cases), while the full lookup path (with higher reliability) handles complex cases, thus mediating between speed and reliability requirements.
Data Source
AI summary
An apparatus comprises a branch target buffer (BTB) to store predicted target addresses of branch instructions. In response to a fetch block address identifying a fetch block comprising two or more program instructions, the BTB performs a lookup to identify whether it stores one or more predicted target addresses for one or more branch instructions in the fetch block. When the BTB is identified in the lookup as storing predicted target addresses for more than one branch instruction in said fetch block, branch target selecting circuitry selects a next fetch block address from among the multiple predicted target addresses returned in the lookup. A shortcut path bypassing the branch target selecting circuitry is provided to forward a predicted target address identified in the lookup as the next fetch block address when a predetermined condition is satisfied.