BTBAS Nitride Trench Liner for Selective Etching and Strain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional trench isolation processes in semiconductor fabrication often result in accidental etching and damage to the liner nitride within the trench due to the non-selective etching of the trench liner material, leading to reduced manufacturing quality and potential performance issues in transistors.
Innovation Solution
Employing a trench liner material, such as bis(t-butylamino)silane-based (BTBAS) nitride, which exhibits a significantly slower etch rate compared to conventional dichlorosilane (DCS) nitride, allowing for more precise control over the etching process and protecting the isolation trench while exerting enhanced tensile strain on active regions for improved transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional DCS nitride is used as trench liner material, then the etching process can be completed, but the liner nitride is accidentally etched and damaged due to non-selective etching
Solution Approach 1:
The patent applies local quality by using different nitride materials with different etch selectivities in different locations: BTBAS nitride in the isolation trench (high etch resistance) and DCS nitride in active regions (high etch responsiveness). This allows the trench liner to resist etching while active region liners are properly removed, resolving the contradiction between etching precision and liner protection.
Solution Approach 2:
The patent changes the material parameter (etch selectivity) of the trench liner from conventional DCS nitride to BTBAS nitride. This parameter change increases the etch resistance by a factor of 5-10x, allowing the liner to survive the etching process that removes active region liners, thus protecting the trench while maintaining manufacturing precision.
2Reliability
If BTBAS nitride is used as trench liner material, then the liner is protected from accidental etching, but the etching process requires longer time to remove active region liners
Solution Approach 1:
By assigning different etch selectivity properties to different locations (BTBAS in trench, DCS in active regions), the patent enables selective removal of active region liners while preserving the trench liner. The etching time is extended only enough to remove the thinner active region liners, not the thicker trench liner, thus minimizing time loss while maintaining protection.
Solution Approach 2:
The patent applies partial action by etching only the active region liners (not the trench liner) during the removal step. The etching process is controlled to remove the necessary amount of material from active regions without excessively attacking the protected trench liner, optimizing the balance between protection and processing time.
3Ease of manufacture
If conventional trench liner material is used, then the fabrication process is simpler, but the transistor performance is reduced due to lower tensile strain
Solution Approach 1:
The patent changes the material composition parameter of the trench liner from DCS nitride to BTBAS nitride. This material substitution provides enhanced tensile strain (500-1500 MPa vs. 200-400 MPa) that improves carrier mobility and transistor performance, while the deposition process remains compatible with existing fabrication equipment and procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision of the fabrication process, reduces accidental etching, and increases carrier mobility in NMOS devices by exerting a higher tensile strain, resulting in higher-quality semiconductor devices with improved performance.
Implementation Method 1
exerting a tensile strain on the active regions adjacent to the isolation trench
Implementation Method 2
exhibits a significantly slower etch rate compared to conventional dichlorosilane (DCS) nitride
Data Source
AI summary
A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein.