BTSV Test Structure for High-Voltage 3D IC Probe Access
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Solution Overview
Problem
The challenge of electronic testing, particularly circuit probe testing, in 3D integrated circuits (ICs) is hindered by the absence of functional conductive lines in the first and second conductive layers due to high-voltage devices, limiting the formation of back-side through-substrate vias (BTSVs), which increases fabrication costs and reduces yield.
Innovation Solution
Incorporating a ring-shaped deep trench isolation (DTI) structure in the semiconductor substrate, with a conductive interconnect structure and BTSVs disposed within its perimeter, allowing electrical coupling to conductive lines in the first conductive layer for effective electronic testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage devices are integrated in the first and second conductive layers, then device functionality is improved, but circuit probe testing becomes impossible due to absence of functional conductive lines
Solution Approach 1:
The patent divides the conductive layers into functional regions (for high-voltage devices) and testing regions (for probe access). By segmenting the substrate into device regions and testing regions, the invention allows high-voltage devices to occupy the functional areas while dedicated testing areas provide access to lower conductive layers for circuit probe testing, thus resolving the contradiction between device functionality and testability
Solution Approach 2:
The patent introduces depth as an additional dimension for testing access by forming through-substrate vias that extend vertically through the substrate to reach conductive lines in lower conductive layers. This vertical dimensionality change allows probe access to internal conductive structures without interfering with the planar high-voltage device layout, enabling both device functionality and circuit probe testing to coexist
2Difficulty of detecting and measuring
If through-substrate vias are formed to enable testing, then testing capability is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent performs preliminary actions by forming testing regions and through-substrate vias during the fabrication process before final device assembly. The testing structures are prepared in advance with conductive lines and via openings created in lower conductive layers, enabling subsequent probe testing without requiring additional complex fabrication steps or post-processing operations
Solution Approach 2:
The patent introduces intermediate testing structures including conductive lines in lower conductive layers and through-substrate vias that act as mediators between the probe and the internal device structures. These intermediary elements provide a pathway for testing signals to reach internal conductive lines without requiring direct access to the high-voltage device regions, simplifying the overall testing architecture
3Productivity
If testing structures are added to the substrate, then yield is improved, but fabrication cost increases
Solution Approach 1:
The patent merges the testing structure fabrication with the existing device fabrication process by using the same substrate, conductive layer formation, and via creation steps. The testing regions share common fabrication infrastructure with the device regions, allowing testing structures to be integrated without requiring separate fabrication lines or additional expensive processing steps, thus improving yield while controlling costs
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first deep trench isolation (DTI) structure in a substrate. A dielectric structure is over the substrate. An interconnect structure is in the dielectric structure. The interconnect structure includes a lower interconnect structure and an upper interconnect structure that are electrically coupled together. The upper interconnect structure includes a plurality of conductive plates. The plurality of conductive plates are vertically stacked and electrically coupled together. A back-side through substrate via (BTSV) is in the substrate and the dielectric structure. The BTSV extends from a conductive feature of the lower interconnect structure through the dielectric structure and the substrate. The conductive feature of the lower interconnect structure is at least partially laterally within a perimeter of the DTI structure. The BTSV is within the perimeter of the DTI structure.