Block Translation Table for Persistent Memory Atomicity

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Solution Overview

Problem

Existing storage-class memory (SCM) systems face challenges in providing sector atomicity guarantees during write operations, especially in scenarios involving power failures, which can result in torn sectors and data corruption.

Innovation Solution

The implementation of a Block Translation Table (BTT) with various modes such as unmodified, modified, and copy BTT, allowing for per-write basis control of physical block address updates, direct access, and in-place operations to ensure sector atomicity and data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the physical block address is changed during a write operation to provide sector atomicity, then data integrity is improved, but the complexity of the storage system increases due to the need for Block Translation Table management

Engineering Contradiction:
Improvesector atomicityVSAvoidBlock Translation Table management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a Block Translation Table (BTT) as an intermediary data structure that maps logical block addresses to physical block addresses. This mediator enables atomic sector updates by allowing the system to remap blocks without exposing the complexity of physical address management to upper layers, thus resolving the contradiction between reliability improvement and system complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent performs preliminary actions by pre-allocating free blocks and pre-computing translation table entries before actual write operations. The BTT is prepared in advance with valid PBA mappings, so that when a write occurs, the atomic update can proceed immediately without complex runtime decisions, reducing the perceived complexity during critical operations

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the Block Translation Table is modified to track physical block addresses for atomic updates, then sector atomicity is provided, but the I/O operation overhead increases

Engineering Contradiction:
Improvesector atomicityVSAvoidI/O operation overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the parameter of the translation table from a simple static mapping to a dynamic structure that includes validity flags and generation counters. This parameter change allows the system to quickly determine whether BTT updates are needed without full table scans, reducing I/O overhead while maintaining atomicity guarantees

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements partial updates to the BTT by only modifying specific entries that are affected by write operations rather than updating the entire table. This selective approach reduces the overhead of BTT management while still providing atomicity for the specific sectors being modified

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If direct access to persistent memory is allowed without BTT remapping, then I/O performance is improved, but sector atomicity guarantees are lost

Engineering Contradiction:
ImproveI/O performanceVSAvoidsector atomicity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent makes the BTT remapping behavior dynamic by providing multiple modes (unmodified BTT, modified BTT, copy BTT) that can be selected based on the specific I/O operation requirements. This dynamic approach allows the system to optimize for performance when atomicity is not critical while maintaining atomicity guarantees when needed, resolving the contradiction between speed and reliability

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3446221B1Adapted block translation table (BTT)
Publication Date: 2020.02.12 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP3446221B1 patent drawingFigure 1
  • EP3446221B1 patent drawingFigure 2
  • EP3446221B1 patent drawingFigure 3

AI summary

Techniques are described for performing a memory operation where direct memory access and logical address translation are implemented. A request for an I/O operation received that includes information indicative of whether a physical memory address may be changed and whether sector atomicity is desired. Based on the information, the requested I/O operation is performed using unmodified Block Translation Table (BTT) where the physical location associated with the requested I/O operation is changed and sector atomicity is provided, or modified BTT where a physical location associated with the requested I/O operation is not changed, or modified BTT where a physical location associated with the requested I/O operation is not changed and atomicity is provided.