Alternating Büchi Automata Simplification for Faster Circuit Verification
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Solution Overview
Problem
The computational inefficiency of formal verification using large alternating Büchi automata in circuit design due to a large number of states and transitions, leading to prolonged processing times and potential failure to converge within time limits.
Innovation Solution
A system transforms alternating Büchi automata into simplified versions with fewer states by merging states representing circuit assertions, eliminating unnecessary transitions, and adjusting acceptance conditions, thereby reducing the number of states and improving verification efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large alternating Büchi automaton is generated based on assertions for formal verification, then the verification coverage is improved, but the computational efficiency deteriorates due to the large number of states and transitions
Solution Approach 1:
The patent merges equivalent states in the alternating Büchi automaton by analyzing state equivalence through symbolic representation and merging states that have identical future behavior. This reduces the total number of states while preserving the automaton's language recognition capability, thereby maintaining verification coverage while improving computational efficiency.
Solution Approach 2:
The patent transforms the automaton representation by changing parameters such as state encoding and transition function representation. By using symbolic representations and optimizing the structure of the transition function, the patent reduces the computational complexity of processing the automaton without affecting its verification capability.
2Productivity
If the number of states in the alternating Büchi automaton is reduced by merging states, then the computational efficiency is improved, but the complexity of the simplification process increases
Solution Approach 1:
The patent performs preliminary analysis of state equivalence before merging, using symbolic representation to identify candidate states for merging. By pre-processing the automaton to mark equivalent states, the patent simplifies the subsequent merging process and avoids the need for complex real-time equivalence checking during state reduction.
Solution Approach 2:
The patent uses symbolic representations and copies of state information to analyze equivalence without directly manipulating the full automaton structure. By working with compressed symbolic representations, the patent reduces the complexity of the simplification process while achieving the same state merging results.
Data Source
AI summary
A system receives assertions representing properties of a circuit design. The system determines a representation of an alternating Büchi automaton based on the assertions. The system transforms the representation of the alternating Büchi automaton to generate a representation of a simplified alternating Büchi automaton. The simplified alternating Büchi automaton has fewer states than the alternating Büchi automaton. One or more states of the simplified alternating Büchi automaton are obtained by merging states of the alternating Büchi automaton representing the assertions of the circuit. The system performs formal verification of the circuit design using the simplified alternating Büchi automaton.